KVM: x86 emulator: drop unused old-style inline emulation
Signed-off-by: Avi Kivity <avi.kivity@gmail.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>hifive-unleashed-5.1
Avi Kivity
Gleb Natapov
parent
b8c0b6ae49
commit
203831e8e4
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@ -284,175 +284,18 @@ static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
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ctxt->regs_valid = 0;
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}
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/*
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* Instruction emulation:
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* Most instructions are emulated directly via a fragment of inline assembly
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* code. This allows us to save/restore EFLAGS and thus very easily pick up
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* any modified flags.
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*/
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#if defined(CONFIG_X86_64)
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#define _LO32 "k" /* force 32-bit operand */
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#define _STK "%%rsp" /* stack pointer */
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#elif defined(__i386__)
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#define _LO32 "" /* force 32-bit operand */
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#define _STK "%%esp" /* stack pointer */
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#endif
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/*
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* These EFLAGS bits are restored from saved value during emulation, and
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* any changes are written back to the saved value after emulation.
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*/
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#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
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/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp) \
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/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
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"movl %"_sav",%"_LO32 _tmp"; " \
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"push %"_tmp"; " \
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"push %"_tmp"; " \
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"movl %"_msk",%"_LO32 _tmp"; " \
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"andl %"_LO32 _tmp",("_STK"); " \
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"pushf; " \
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"notl %"_LO32 _tmp"; " \
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"andl %"_LO32 _tmp",("_STK"); " \
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"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
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"pop %"_tmp"; " \
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"orl %"_LO32 _tmp",("_STK"); " \
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"popf; " \
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"pop %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
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#define _POST_EFLAGS(_sav, _msk, _tmp) \
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/* _sav |= EFLAGS & _msk; */ \
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"pushf; " \
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"pop %"_tmp"; " \
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"andl %"_msk",%"_LO32 _tmp"; " \
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"orl %"_LO32 _tmp",%"_sav"; "
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#ifdef CONFIG_X86_64
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#define ON64(x) x
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#else
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#define ON64(x)
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#endif
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#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
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do { \
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__asm__ __volatile__ ( \
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_PRE_EFLAGS("0", "4", "2") \
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_op _suffix " %"_x"3,%1; " \
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_POST_EFLAGS("0", "4", "2") \
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: "=m" ((ctxt)->eflags), \
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"+q" (*(_dsttype*)&(ctxt)->dst.val), \
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"=&r" (_tmp) \
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: _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
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} while (0)
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/* Raw emulation: instruction has two explicit operands. */
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#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
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do { \
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unsigned long _tmp; \
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\
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switch ((ctxt)->dst.bytes) { \
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case 2: \
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____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
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break; \
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case 4: \
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____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
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break; \
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case 8: \
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ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
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break; \
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} \
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} while (0)
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#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
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do { \
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unsigned long _tmp; \
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switch ((ctxt)->dst.bytes) { \
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case 1: \
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____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
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break; \
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default: \
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__emulate_2op_nobyte(ctxt, _op, \
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_wx, _wy, _lx, _ly, _qx, _qy); \
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break; \
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} \
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} while (0)
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/* Source operand is byte-sized and may be restricted to just %cl. */
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#define emulate_2op_SrcB(ctxt, _op) \
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__emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
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/* Source operand is byte, word, long or quad sized. */
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#define emulate_2op_SrcV(ctxt, _op) \
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__emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
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/* Source operand is word, long or quad sized. */
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#define emulate_2op_SrcV_nobyte(ctxt, _op) \
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__emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
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/* Instruction has three operands and one operand is stored in ECX register */
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#define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
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do { \
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unsigned long _tmp; \
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_type _clv = (ctxt)->src2.val; \
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_type _srcv = (ctxt)->src.val; \
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_type _dstv = (ctxt)->dst.val; \
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\
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__asm__ __volatile__ ( \
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_PRE_EFLAGS("0", "5", "2") \
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_op _suffix " %4,%1 \n" \
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_POST_EFLAGS("0", "5", "2") \
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: "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
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: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
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); \
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\
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(ctxt)->src2.val = (unsigned long) _clv; \
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(ctxt)->src2.val = (unsigned long) _srcv; \
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(ctxt)->dst.val = (unsigned long) _dstv; \
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} while (0)
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#define emulate_2op_cl(ctxt, _op) \
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do { \
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switch ((ctxt)->dst.bytes) { \
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case 2: \
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__emulate_2op_cl(ctxt, _op, "w", u16); \
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break; \
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case 4: \
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__emulate_2op_cl(ctxt, _op, "l", u32); \
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break; \
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case 8: \
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ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
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break; \
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} \
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} while (0)
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#define __emulate_1op(ctxt, _op, _suffix) \
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do { \
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unsigned long _tmp; \
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\
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__asm__ __volatile__ ( \
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_PRE_EFLAGS("0", "3", "2") \
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_op _suffix " %1; " \
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_POST_EFLAGS("0", "3", "2") \
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: "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
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"=&r" (_tmp) \
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: "i" (EFLAGS_MASK)); \
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} while (0)
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/* Instruction has only one explicit operand (no source operand). */
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#define emulate_1op(ctxt, _op) \
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do { \
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switch ((ctxt)->dst.bytes) { \
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case 1: __emulate_1op(ctxt, _op, "b"); break; \
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case 2: __emulate_1op(ctxt, _op, "w"); break; \
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case 4: __emulate_1op(ctxt, _op, "l"); break; \
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case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
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} \
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} while (0)
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static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
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#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
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@ -571,47 +414,6 @@ FOP_END;
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FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
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FOP_END;
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#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
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do { \
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unsigned long _tmp; \
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ulong *rax = &ctxt->dst.val; \
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ulong *rdx = &ctxt->src.val; \
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\
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__asm__ __volatile__ ( \
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_PRE_EFLAGS("0", "5", "1") \
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"1: \n\t" \
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_op _suffix " %6; " \
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"2: \n\t" \
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_POST_EFLAGS("0", "5", "1") \
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".pushsection .fixup,\"ax\" \n\t" \
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"3: movb $1, %4 \n\t" \
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"jmp 2b \n\t" \
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".popsection \n\t" \
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_ASM_EXTABLE(1b, 3b) \
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: "=m" ((ctxt)->eflags), "=&r" (_tmp), \
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"+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
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: "i" (EFLAGS_MASK), "m" ((ctxt)->src2.val)); \
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} while (0)
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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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#define emulate_1op_rax_rdx(ctxt, _op, _ex) \
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do { \
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switch((ctxt)->src.bytes) { \
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case 1: \
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__emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
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break; \
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case 2: \
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__emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
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break; \
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case 4: \
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__emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
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break; \
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case 8: ON64( \
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__emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
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break; \
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} \
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} while (0)
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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
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enum x86_intercept intercept,
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enum x86_intercept_stage stage)
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