ARM: SoC fixes for v4.11
- A couple of OMAP 4.11 regression fixes, including a boot regression for SmartReflex, hypervisor mode in thumb2 mode, and reference counting of device nodes - A fix for cpu_idle on at91 - Minor DT fixes on across several platforms: sunxi, bcm53xx, at91, nsp, ns2, ux500, omap - A fix to correct an API change in the reset controllers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUAWNWBrGCrR//JCVInAQJE/xAArSDx+6i7On53k3QfxkR1mONHrEOlXhlP VbTeBfkYtYB08Pgq99QVJE5qYK2N5w2664UNbgs+KKYnYJTNl0G6EW1l7oj+21M+ xg3e6ctdfeztYeU34q7D2TxzP/EBRHdbpEuT+JHuQOWFYNfGAj2vSt2cdPUael/Q D4s4BgeM1dIOzN3z3AvuQpqIhLedVRFAGYAaalKXiwREYUVDgnqhHCPWChVnSQMR gnNDYcb5ZxCaELH9gkdVqyfdlScw9juKMg5v7e7KizhBUqOGBT0bguLC9Kfh3mDO tIJGwkuqWvc5tAKuAcGklIVOzP8Wtcq0ObrFzLczy6Waf+6aaQl5J8Uw85UR/zg4 44AHzk++apXTCDlrRzQZIkvaN9TmOBr65qrW1rnqVN72FRS3arDuMV1rEFRdZy2x riXmJmENWo+sakst4fTS0QY+/GlPDB8Md4X++Vkl3DgWFgiiBTcPbJCEazsFVip+ QQzWfXTSB98bCVUuYr5eZgMlPYHrd1ZQIbgzlzIkdUuZ4XCe4MGw88km6TqviBwf dduNKnFctkrLAgM3V8rXZBQsZqJHRDmpOfSZ+9XtGYggy83g5FLbkp9h6Ws66SbI KCgLzV0THCs/gKLMeDqFerO1xQzxN84pd+YKetnD1RU+5bo98DMUkqgFn+cZyCFA dlImlZcN7Pc= =zKIg -----END PGP SIGNATURE----- Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Arnd Bergmann: - a couple of OMAP 4.11 regression fixes, including a boot regression for SmartReflex, hypervisor mode in thumb2 mode, and reference counting of device nodes - a fix for cpu_idle on at91 - minor DT fixes on across several platforms: sunxi, bcm53xx, at91, nsp, ns2, ux500, omap - a fix to correct an API change in the reset controllers * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits) arm64: dts: NS2: Add dma-coherent to relevant DT entries reset: fix optional reset_control_get stubs to return NULL ARM: sun8i: a23/a33: drop bl_en_pin GPIO pinmux in reference design DTSI ARM: dts: sun7i: lamobo-r1: Fix CPU port RGMII settings ARM: dts: NSP: GPIO reboot open-source ARM: at91: pm: cpu_idle: switch DDR to power-down mode ARM: dts: add the AB8500 clocks to the device tree ARM: dts: imx6sx-udoo-neo: Fix reboot hang ARM: sun8i: Fix the mali clock rate ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags ARM: dts: BCM5301X: Fix memory start address ARM: dts: BCM5301X: Fix UARTs on bcm953012k Revert "ARM: at91/dt: sama5d2: Use new compatible for ohci node" ARM: OMAP2+: Release device node after it is no longer needed. ARM: OMAP2+: Fix device node reference counts ARM: OMAP2+: Remove legacy gpmc-nand.c ARM: OMAP2+: gpmc-onenand: propagate error on initialization failure ARM: dts: am335x-pcm953: Fix legacy wakeup source binding ARM: omap2plus_defconfig: Enable INPUT_MOUSEDEV as loadable modules ARM: dts: am57xx-idk: tpic2810 is on I2C bus, not SPI ...hifive-unleashed-5.1
Linus Torvalds
commit
2056b7c7df
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@ -63,14 +63,14 @@
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label = "home";
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linux,code = <KEY_HOME>;
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gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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gpio-key,wakeup;
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wakeup-source;
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};
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button@1 {
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label = "menu";
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linux,code = <KEY_MENU>;
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gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
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gpio-key,wakeup;
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wakeup-source;
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};
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};
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@ -315,6 +315,13 @@
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/* ID & VBUS GPIOs provided in board dts */
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};
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};
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tpic2810: tpic2810@60 {
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compatible = "ti,tpic2810";
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reg = <0x60>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&mcspi3 {
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@ -330,13 +337,6 @@
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spi-max-frequency = <1000000>;
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spi-cpol;
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};
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tpic2810: tpic2810@60 {
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compatible = "ti,tpic2810";
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reg = <0x60>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&uart3 {
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@ -66,14 +66,14 @@
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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};
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local-timer@20600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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};
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@ -48,15 +48,14 @@
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};
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memory {
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reg = <0x00000000 0x10000000>;
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reg = <0x80000000 0x10000000>;
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};
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};
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&uart0 {
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clock-frequency = <62499840>;
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status = "okay";
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};
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&uart1 {
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clock-frequency = <62499840>;
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status = "okay";
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 31 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -55,6 +55,7 @@
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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};
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@ -121,11 +121,6 @@
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};
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};
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&cpu0 {
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arm-supply = <&sw1a_reg>;
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soc-supply = <&sw1c_reg>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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@ -266,7 +266,7 @@
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};
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usb1: ohci@00400000 {
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compatible = "atmel,sama5d2-ohci", "usb-ohci";
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compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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reg = <0x00400000 0x100000>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
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clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
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@ -14,6 +14,7 @@
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#include <dt-bindings/mfd/dbx500-prcmu.h>
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#include <dt-bindings/arm/ux500_pm_domains.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/ste-ab8500.h>
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#include "skeleton.dtsi"
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/ {
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@ -603,6 +604,11 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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ab8500_clock: clock-controller {
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compatible = "stericsson,ab8500-clk";
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#clock-cells = <1>;
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};
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ab8500_gpio: ab8500-gpio {
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compatible = "stericsson,ab8500-gpio";
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gpio-controller;
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@ -686,6 +692,8 @@
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ab8500-pwm {
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compatible = "stericsson,ab8500-pwm";
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clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
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clock-names = "intclk";
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};
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ab8500-debugfs {
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@ -700,6 +708,9 @@
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V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
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V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
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clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
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clock-names = "audioclk";
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stericsson,earpeice-cmv = <950>; /* Units in mV. */
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};
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@ -1095,6 +1106,14 @@
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status = "disabled";
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};
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sound {
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compatible = "stericsson,snd-soc-mop500";
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stericsson,cpu-dai = <&msp1 &msp3>;
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stericsson,audio-codec = <&codec>;
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clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
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clock-names = "sysclk", "ulpclk", "intclk";
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};
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msp0: msp@80123000 {
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compatible = "stericsson,ux500-msp-i2s";
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reg = <0x80123000 0x1000>;
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@ -186,15 +186,6 @@
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status = "okay";
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};
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sound {
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compatible = "stericsson,snd-soc-mop500";
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stericsson,cpu-dai = <&msp1 &msp3>;
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stericsson,audio-codec = <&codec>;
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clocks = <&prcmu_clk PRCMU_SYSCLK>;
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clock-names = "sysclk";
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};
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msp0: msp@80123000 {
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pinctrl-names = "default";
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pinctrl-0 = <&msp0_default_mode>;
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@ -159,15 +159,6 @@
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"", "", "", "", "", "", "", "";
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};
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sound {
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compatible = "stericsson,snd-soc-mop500";
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stericsson,cpu-dai = <&msp1 &msp3>;
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stericsson,audio-codec = <&codec>;
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clocks = <&prcmu_clk PRCMU_SYSCLK>;
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clock-names = "sysclk";
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};
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msp0: msp@80123000 {
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pinctrl-names = "default";
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pinctrl-0 = <&msp0_default_mode>;
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@ -167,7 +167,7 @@
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reg = <8>;
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label = "cpu";
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ethernet = <&gmac>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-txid";
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fixed-link {
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speed = <1000>;
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full-duplex;
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@ -495,7 +495,7 @@
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resets = <&ccu RST_BUS_GPU>;
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assigned-clocks = <&ccu CLK_GPU>;
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assigned-clock-rates = <408000000>;
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assigned-clock-rates = <384000000>;
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};
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gic: interrupt-controller@01c81000 {
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@ -50,8 +50,6 @@
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backlight: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&bl_en_pin>;
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pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
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brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
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default-brightness-level = <8>;
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@ -93,11 +91,6 @@
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};
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&pio {
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bl_en_pin: bl_en_pin@0 {
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pins = "PH6";
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function = "gpio_in";
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};
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mmc0_cd_pin: mmc0_cd_pin@0 {
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pins = "PB4";
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function = "gpio_in";
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@ -188,6 +188,7 @@ CONFIG_WL12XX=m
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CONFIG_WL18XX=m
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CONFIG_WLCORE_SPI=m
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CONFIG_WLCORE_SDIO=m
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CONFIG_INPUT_MOUSEDEV=m
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CONFIG_INPUT_JOYDEV=m
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CONFIG_INPUT_EVDEV=m
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CONFIG_KEYBOARD_ATKBD=m
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@ -289,6 +289,22 @@ static void at91_ddr_standby(void)
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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static void sama5d3_ddr_standby(void)
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{
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u32 lpr0;
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u32 saved_lpr0;
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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||||
|
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cpu_do_idle();
|
||||
|
||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
|
||||
}
|
||||
|
||||
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
|
||||
* remember.
|
||||
*/
|
||||
|
|
@ -323,7 +339,7 @@ static const struct of_device_id const ramc_ids[] __initconst = {
|
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{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
|
||||
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
|
||||
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
|
||||
{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
|
||||
{ .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
|
||||
{ /*sentinel*/ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -241,6 +241,3 @@ obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
|
|||
|
||||
onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
|
||||
obj-y += $(onenand-m) $(onenand-y)
|
||||
|
||||
nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
|
||||
obj-y += $(nand-m) $(nand-y)
|
||||
|
|
|
|||
|
|
@ -1,154 +0,0 @@
|
|||
/*
|
||||
* gpmc-nand.c
|
||||
*
|
||||
* Copyright (C) 2009 Texas Instruments
|
||||
* Vimal Singh <vimalsingh@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/omap-gpmc.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/platform_data/mtd-nand-omap2.h>
|
||||
|
||||
#include <asm/mach/flash.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* minimum size for IO mapping */
|
||||
#define NAND_IO_SIZE 4
|
||||
|
||||
static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
|
||||
{
|
||||
/* platforms which support all ECC schemes */
|
||||
if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
|
||||
soc_is_omap54xx() || soc_is_dra7xx())
|
||||
return 1;
|
||||
|
||||
if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW ||
|
||||
ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) {
|
||||
if (cpu_is_omap24xx())
|
||||
return 0;
|
||||
else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0))
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* OMAP3xxx do not have ELM engine, so cannot support ECC schemes
|
||||
* which require H/W based ECC error detection */
|
||||
if ((cpu_is_omap34xx() || cpu_is_omap3630()) &&
|
||||
((ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
|
||||
(ecc_opt == OMAP_ECC_BCH8_CODE_HW)))
|
||||
return 0;
|
||||
|
||||
/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
|
||||
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
|
||||
ecc_opt == OMAP_ECC_HAM1_CODE_SW)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This function will go away once the device-tree convertion is complete */
|
||||
static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data,
|
||||
struct gpmc_settings *s)
|
||||
{
|
||||
/* Enable RD PIN Monitoring Reg */
|
||||
if (gpmc_nand_data->dev_ready) {
|
||||
s->wait_on_read = true;
|
||||
s->wait_on_write = true;
|
||||
}
|
||||
|
||||
if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
|
||||
s->device_width = GPMC_DEVWIDTH_16BIT;
|
||||
else
|
||||
s->device_width = GPMC_DEVWIDTH_8BIT;
|
||||
}
|
||||
|
||||
int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
|
||||
struct gpmc_timings *gpmc_t)
|
||||
{
|
||||
int err = 0;
|
||||
struct gpmc_settings s;
|
||||
struct platform_device *pdev;
|
||||
struct resource gpmc_nand_res[] = {
|
||||
{ .flags = IORESOURCE_MEM, },
|
||||
{ .flags = IORESOURCE_IRQ, },
|
||||
{ .flags = IORESOURCE_IRQ, },
|
||||
};
|
||||
|
||||
BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
|
||||
|
||||
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
|
||||
(unsigned long *)&gpmc_nand_res[0].start);
|
||||
if (err < 0) {
|
||||
pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
|
||||
gpmc_nand_data->cs, err);
|
||||
return err;
|
||||
}
|
||||
gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
|
||||
gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
|
||||
gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
|
||||
|
||||
memset(&s, 0, sizeof(struct gpmc_settings));
|
||||
gpmc_set_legacy(gpmc_nand_data, &s);
|
||||
|
||||
s.device_nand = true;
|
||||
|
||||
if (gpmc_t) {
|
||||
err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s);
|
||||
if (err < 0) {
|
||||
pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
|
||||
err = gpmc_configure(GPMC_CONFIG_WP, 0);
|
||||
if (err < 0)
|
||||
goto out_free_cs;
|
||||
|
||||
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
|
||||
pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n");
|
||||
err = -EINVAL;
|
||||
goto out_free_cs;
|
||||
}
|
||||
|
||||
|
||||
pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs);
|
||||
if (pdev) {
|
||||
err = platform_device_add_resources(pdev, gpmc_nand_res,
|
||||
ARRAY_SIZE(gpmc_nand_res));
|
||||
if (!err)
|
||||
pdev->dev.platform_data = gpmc_nand_data;
|
||||
} else {
|
||||
err = -ENOMEM;
|
||||
}
|
||||
if (err)
|
||||
goto out_free_pdev;
|
||||
|
||||
err = platform_device_add(pdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Unable to register NAND device\n");
|
||||
goto out_free_pdev;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_pdev:
|
||||
platform_device_put(pdev);
|
||||
out_free_cs:
|
||||
gpmc_cs_free(gpmc_nand_data->cs);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
@ -367,7 +367,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
|
|||
return ret;
|
||||
}
|
||||
|
||||
void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
||||
int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
||||
{
|
||||
int err;
|
||||
struct device *dev = &gpmc_onenand_device.dev;
|
||||
|
|
@ -393,15 +393,17 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
|
|||
if (err < 0) {
|
||||
dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
|
||||
gpmc_onenand_data->cs, err);
|
||||
return;
|
||||
return err;
|
||||
}
|
||||
|
||||
gpmc_onenand_resource.end = gpmc_onenand_resource.start +
|
||||
ONENAND_IO_SIZE - 1;
|
||||
|
||||
if (platform_device_register(&gpmc_onenand_device) < 0) {
|
||||
err = platform_device_register(&gpmc_onenand_device);
|
||||
if (err) {
|
||||
dev_err(dev, "Unable to register OneNAND device\n");
|
||||
gpmc_cs_free(gpmc_onenand_data->cs);
|
||||
return;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
|
||||
#include <linux/linkage.h>
|
||||
#include <linux/init.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#include "omap44xx.h"
|
||||
|
||||
|
|
@ -66,7 +67,7 @@ wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
|||
cmp r0, r4
|
||||
bne wait_2
|
||||
ldr r12, =API_HYP_ENTRY
|
||||
adr r0, hyp_boot
|
||||
badr r0, hyp_boot
|
||||
smc #0
|
||||
hyp_boot:
|
||||
b omap_secondary_startup
|
||||
|
|
|
|||
|
|
@ -2112,11 +2112,20 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
|
|||
};
|
||||
|
||||
/* L4 CORE -> SR1 interface */
|
||||
static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP34XX_SR1_BASE,
|
||||
.pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_sr1_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -2124,15 +2133,25 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
|
|||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap36xx_sr1_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr1_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* L4 CORE -> SR1 interface */
|
||||
static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP34XX_SR2_BASE,
|
||||
.pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
|
||||
.flags = ADDR_TYPE_RT,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
|
||||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap34xx_sr2_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -2140,6 +2159,7 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
|
|||
.master = &omap3xxx_l4_core_hwmod,
|
||||
.slave = &omap36xx_sr2_hwmod,
|
||||
.clk = "sr_l4_ick",
|
||||
.addr = omap3_sr2_addr_space,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
|
|
@ -3111,16 +3131,20 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
|
|||
* Return: 0 if device named @dev_name is not likely to be accessible,
|
||||
* or 1 if it is likely to be accessible.
|
||||
*/
|
||||
static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
|
||||
const char *dev_name)
|
||||
static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
|
||||
const char *dev_name)
|
||||
{
|
||||
struct device_node *node;
|
||||
bool available;
|
||||
|
||||
if (!bus)
|
||||
return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
|
||||
return omap_type() == OMAP2_DEVICE_TYPE_GP;
|
||||
|
||||
if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
|
||||
return 1;
|
||||
node = of_get_child_by_name(bus, dev_name);
|
||||
available = of_device_is_available(node);
|
||||
of_node_put(node);
|
||||
|
||||
return 0;
|
||||
return available;
|
||||
}
|
||||
|
||||
int __init omap3xxx_hwmod_init(void)
|
||||
|
|
@ -3189,15 +3213,20 @@ int __init omap3xxx_hwmod_init(void)
|
|||
|
||||
if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
|
||||
r = omap_hwmod_register_links(h_sham);
|
||||
if (r < 0)
|
||||
if (r < 0) {
|
||||
of_node_put(bus);
|
||||
return r;
|
||||
}
|
||||
}
|
||||
|
||||
if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
|
||||
r = omap_hwmod_register_links(h_aes);
|
||||
if (r < 0)
|
||||
if (r < 0) {
|
||||
of_node_put(bus);
|
||||
return r;
|
||||
}
|
||||
}
|
||||
of_node_put(bus);
|
||||
|
||||
/*
|
||||
* Register hwmod links specific to certain ES levels of a
|
||||
|
|
|
|||
|
|
@ -114,6 +114,7 @@
|
|||
pcie0: pcie@20020000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0 0x20020000 0 0x1000>;
|
||||
dma-coherent;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
|
|
@ -144,6 +145,7 @@
|
|||
pcie4: pcie@50020000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0 0x50020000 0 0x1000>;
|
||||
dma-coherent;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
|
|
@ -174,6 +176,7 @@
|
|||
pcie8: pcie@60c00000 {
|
||||
compatible = "brcm,iproc-pcie-paxc";
|
||||
reg = <0 0x60c00000 0 0x1000>;
|
||||
dma-coherent;
|
||||
linux,pci-domain = <8>;
|
||||
|
||||
bus-range = <0x0 0x1>;
|
||||
|
|
@ -203,6 +206,7 @@
|
|||
<0x61030000 0x100>;
|
||||
reg-names = "amac_base", "idm_base", "nicpm_base";
|
||||
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
phy-handle = <&gphy0>;
|
||||
phy-mode = "rgmii";
|
||||
status = "disabled";
|
||||
|
|
@ -213,6 +217,7 @@
|
|||
reg = <0x612c0000 0x445>; /* PDC FS0 regs */
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
dma-coherent;
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
||||
|
|
@ -222,6 +227,7 @@
|
|||
reg = <0x612e0000 0x445>; /* PDC FS1 regs */
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
dma-coherent;
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
||||
|
|
@ -231,6 +237,7 @@
|
|||
reg = <0x61300000 0x445>; /* PDC FS2 regs */
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
dma-coherent;
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
||||
|
|
@ -240,6 +247,7 @@
|
|||
reg = <0x61320000 0x445>; /* PDC FS3 regs */
|
||||
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
dma-coherent;
|
||||
brcm,rx-status-len = <32>;
|
||||
brcm,use-bcm-hdr;
|
||||
};
|
||||
|
|
@ -644,6 +652,7 @@
|
|||
sata: ahci@663f2000 {
|
||||
compatible = "brcm,iproc-ahci", "generic-ahci";
|
||||
reg = <0x663f2000 0x1000>;
|
||||
dma-coherent;
|
||||
reg-names = "ahci";
|
||||
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -667,6 +676,7 @@
|
|||
compatible = "brcm,sdhci-iproc-cygnus";
|
||||
reg = <0x66420000 0x100>;
|
||||
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
bus-width = <8>;
|
||||
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
|
||||
status = "disabled";
|
||||
|
|
@ -676,6 +686,7 @@
|
|||
compatible = "brcm,sdhci-iproc-cygnus";
|
||||
reg = <0x66430000 0x100>;
|
||||
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-coherent;
|
||||
bus-width = <8>;
|
||||
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -1947,9 +1947,7 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
|
|||
if (!of_property_read_u32(child, "dma-channel", &val))
|
||||
gpmc_onenand_data->dma_channel = val;
|
||||
|
||||
gpmc_onenand_init(gpmc_onenand_data);
|
||||
|
||||
return 0;
|
||||
return gpmc_onenand_init(gpmc_onenand_data);
|
||||
}
|
||||
#else
|
||||
static int gpmc_probe_onenand_child(struct platform_device *pdev,
|
||||
|
|
|
|||
|
|
@ -76,22 +76,12 @@ struct gpmc_timings;
|
|||
struct omap_nand_platform_data;
|
||||
struct omap_onenand_platform_data;
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
|
||||
extern int gpmc_nand_init(struct omap_nand_platform_data *d,
|
||||
struct gpmc_timings *gpmc_t);
|
||||
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
|
||||
extern int gpmc_onenand_init(struct omap_onenand_platform_data *d);
|
||||
#else
|
||||
static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
|
||||
struct gpmc_timings *gpmc_t)
|
||||
#define board_onenand_data NULL
|
||||
static inline int gpmc_onenand_init(struct omap_onenand_platform_data *d)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
|
||||
extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
|
||||
#else
|
||||
#define board_onenand_data NULL
|
||||
static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -31,31 +31,26 @@ static inline int device_reset_optional(struct device *dev)
|
|||
|
||||
static inline int reset_control_reset(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int reset_control_assert(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int reset_control_deassert(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int reset_control_status(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void reset_control_put(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
static inline int __must_check device_reset(struct device *dev)
|
||||
|
|
@ -74,14 +69,14 @@ static inline struct reset_control *__of_reset_control_get(
|
|||
const char *id, int index, bool shared,
|
||||
bool optional)
|
||||
{
|
||||
return ERR_PTR(-ENOTSUPP);
|
||||
return optional ? NULL : ERR_PTR(-ENOTSUPP);
|
||||
}
|
||||
|
||||
static inline struct reset_control *__devm_reset_control_get(
|
||||
struct device *dev, const char *id,
|
||||
int index, bool shared, bool optional)
|
||||
{
|
||||
return ERR_PTR(-ENOTSUPP);
|
||||
return optional ? NULL : ERR_PTR(-ENOTSUPP);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RESET_CONTROLLER */
|
||||
|
|
|
|||
Loading…
Reference in New Issue