drm/amd/pp: Remove the same struct define in powerplay
delete the same struct define in powerplay, share the struct with display. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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70b63170c3
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@ -23,6 +23,8 @@
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#ifndef _DM_PP_INTERFACE_
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#define _DM_PP_INTERFACE_
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#include "dm_services_types.h"
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#define PP_MAX_CLOCK_LEVELS 16
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enum amd_pp_display_config_type{
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@ -189,39 +191,4 @@ struct pp_display_clock_request {
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uint32_t clock_freq_in_khz;
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};
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#define PP_MAX_WM_SETS 4
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enum pp_wm_set_id {
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DC_WM_SET_A = 0,
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DC_WM_SET_B,
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DC_WM_SET_C,
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DC_WM_SET_D,
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DC_WM_SET_INVALID = 0xffff,
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};
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struct pp_wm_set_with_dmif_clock_range_soc15 {
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enum pp_wm_set_id wm_set_id;
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uint32_t wm_min_dcefclk_in_khz;
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uint32_t wm_max_dcefclk_in_khz;
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uint32_t wm_min_memclk_in_khz;
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uint32_t wm_max_memclk_in_khz;
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};
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struct pp_wm_set_with_mcif_clock_range_soc15 {
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enum pp_wm_set_id wm_set_id;
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uint32_t wm_min_socclk_in_khz;
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uint32_t wm_max_socclk_in_khz;
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uint32_t wm_min_memclk_in_khz;
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uint32_t wm_max_memclk_in_khz;
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};
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struct pp_wm_sets_with_clock_ranges_soc15 {
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uint32_t num_wm_sets_dmif;
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uint32_t num_wm_sets_mcif;
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struct pp_wm_set_with_dmif_clock_range_soc15
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wm_sets_dmif[PP_MAX_WM_SETS];
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struct pp_wm_set_with_mcif_clock_range_soc15
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wm_sets_mcif[PP_MAX_WM_SETS];
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};
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#endif /* _DM_PP_INTERFACE_ */
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@ -1111,7 +1111,7 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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void *clock_ranges)
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{
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struct smu10_hwmgr *data = hwmgr->backend;
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
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Watermarks_t *table = &(data->water_marks_table);
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int result = 0;
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@ -652,7 +652,7 @@ int smu_get_voltage_dependency_table_ppt_v1(
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}
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int smu_set_watermarks_for_clocks_ranges(void *wt_table,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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{
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uint32_t i;
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struct watermarks *table = wt_table;
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@ -660,49 +660,49 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,
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if (!table || !wm_with_clock_ranges)
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return -EINVAL;
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if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || wm_with_clock_ranges->num_wm_sets_mcif > 4)
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if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4)
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return -EINVAL;
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for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
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for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
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table->WatermarkRow[1][i].MinClock =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) /
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1000);
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table->WatermarkRow[1][i].MaxClock =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
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(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) /
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100);
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table->WatermarkRow[1][i].MinUclk =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
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1000);
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table->WatermarkRow[1][i].MaxUclk =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
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1000);
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table->WatermarkRow[1][i].WmSetting = (uint8_t)
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wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
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wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
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}
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for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
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for (i = 0; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) {
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table->WatermarkRow[0][i].MinClock =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) /
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1000);
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table->WatermarkRow[0][i].MaxClock =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) /
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1000);
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table->WatermarkRow[0][i].MinUclk =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) /
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1000);
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table->WatermarkRow[0][i].MaxUclk =
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cpu_to_le16((uint16_t)
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(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
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100);
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(wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) /
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1000);
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table->WatermarkRow[0][i].WmSetting = (uint8_t)
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wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
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wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
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}
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return 0;
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}
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@ -107,7 +107,7 @@ int smu_get_voltage_dependency_table_ppt_v1(
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
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int smu_set_watermarks_for_clocks_ranges(void *wt_table,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
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#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
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@ -4197,7 +4197,7 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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void *clock_range)
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{
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struct vega10_hwmgr *data = hwmgr->backend;
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
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Watermarks_t *table = &(data->smc_state_table.water_marks_table);
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int result = 0;
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@ -1785,7 +1785,7 @@ static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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{
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struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
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Watermarks_t *table = &(data->smc_state_table.water_marks_table);
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
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struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
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if (!data->registry_data.disable_water_mark &&
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data->smu_features[GNLD_DPM_DCEFCLK].supported &&
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