redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

serial: sirf: move to writel for TXFIFO instead of writeb 

All SiRFSoC UART registers are in 32-bits. If we use writeb for
TXFIFO, actually all of 32-bits are still written, for TXTIFO,
only low 8-bits are valid, so in prima2&atlas6, this causes no
problem.
But in the new atlas7, using writeb to write UART registers will
cause an imprecise data abort as HW does check the "wrong" writeb.
So move to writel and this also makes the code consistent with
sirfsoc_uart_pio_tx_chars() in which we use writel.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.1
Barry Song 2014-05-05 08:05:51 +08:00 committed by Greg Kroah-Hartman
parent 717e1cb22f
commit 205c384f73
2 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/tty/serial/sirfsoc_uart.c
View File

@ -1228,7 +1228,7 @@ static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
while (rd_regl(port,
ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
cpu_relax();
wr_regb(port, ureg->sirfsoc_tx_fifo_data, ch);
wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
}
static void sirfsoc_uart_console_write(struct console *co, const char *s,

2
drivers/tty/serial/sirfsoc_uart.h
View File

@ -441,9 +441,7 @@ struct sirfsoc_uart_port {
/* Register Access Control */
#define portaddr(port, reg) ((port)->membase + (reg))
#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
/* UART Port Mask */