drm/radeon/r600: fix offset handling in CS parser
Need add reloc offset to the offset in the actual packet. Fixes use of the DRAW_INDEX packet by the 3D driver. [airlied: modified first one where idx_value == ib[idx+0] Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
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@ -380,7 +380,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
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return -EINVAL;
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}
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ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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break;
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case PACKET3_DRAW_INDEX_AUTO:
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if (pkt->count != 1) {
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@ -408,7 +408,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
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return -EINVAL;
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}
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ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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}
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break;
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case PACKET3_SURFACE_SYNC:
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@ -439,7 +439,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
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return -EINVAL;
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}
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ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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}
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break;
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case PACKET3_EVENT_WRITE_EOP:
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@ -453,7 +453,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
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return -EINVAL;
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}
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ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
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ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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break;
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case PACKET3_SET_CONFIG_REG:
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start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
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@ -575,7 +575,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
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return -EINVAL;
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}
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ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
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ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
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break;
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case SQ_TEX_VTX_INVALID_TEXTURE:
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case SQ_TEX_VTX_INVALID_BUFFER:
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