Blackfin arch: rename MAX_BLACKFIN_DMA_CHANNEL to MAX_DMA_CHANNELS to match everyone else
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
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3e706cfcce
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211daf9d72
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@ -201,6 +201,6 @@ void *dma_memcpy(void *dest, const void *src, size_t count);
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void *safe_dma_memcpy(void *dest, const void *src, size_t count);
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void *safe_dma_memcpy(void *dest, const void *src, size_t count);
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extern int channel2irq(unsigned int channel);
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extern int channel2irq(unsigned int channel);
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extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
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extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
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#endif
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#endif
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@ -44,7 +44,7 @@
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* Global Variables
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* Global Variables
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***************************************************************************/
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***************************************************************************/
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static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
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static struct dma_channel dma_ch[MAX_DMA_CHANNELS];
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/*------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------
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* Set the Buffer Clear bit in the Configuration register of specific DMA
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* Set the Buffer Clear bit in the Configuration register of specific DMA
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@ -63,7 +63,7 @@ static int __init blackfin_dma_init(void)
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printk(KERN_INFO "Blackfin DMA Controller\n");
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printk(KERN_INFO "Blackfin DMA Controller\n");
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for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
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for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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dma_ch[i].chan_status = DMA_CHANNEL_FREE;
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dma_ch[i].chan_status = DMA_CHANNEL_FREE;
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dma_ch[i].regs = dma_io_base_addr[i];
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dma_ch[i].regs = dma_io_base_addr[i];
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mutex_init(&(dma_ch[i].dmalock));
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mutex_init(&(dma_ch[i].dmalock));
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@ -87,7 +87,7 @@ static int proc_dma_show(struct seq_file *m, void *v)
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{
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{
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int i;
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int i;
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for (i = 0 ; i < MAX_BLACKFIN_DMA_CHANNEL; ++i)
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for (i = 0 ; i < MAX_DMA_CHANNELS; ++i)
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if (dma_ch[i].chan_status != DMA_CHANNEL_FREE)
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if (dma_ch[i].chan_status != DMA_CHANNEL_FREE)
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seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
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seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
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@ -175,7 +175,7 @@ EXPORT_SYMBOL(request_dma);
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int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
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int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
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{
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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&& channel < MAX_DMA_CHANNELS));
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if (callback != NULL) {
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if (callback != NULL) {
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int ret_val;
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int ret_val;
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@ -200,7 +200,7 @@ void free_dma(unsigned int channel)
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{
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{
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pr_debug("freedma() : BEGIN \n");
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pr_debug("freedma() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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&& channel < MAX_DMA_CHANNELS));
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/* Halt the DMA */
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/* Halt the DMA */
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disable_dma(channel);
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disable_dma(channel);
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@ -418,7 +418,7 @@ int blackfin_dma_suspend(void)
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#ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */
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#ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */
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for (i = 0; i <= CH_MEM_STREAM3_SRC; i++) {
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for (i = 0; i <= CH_MEM_STREAM3_SRC; i++) {
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#else
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#else
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for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
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for (i = 0; i < MAX_DMA_CHANNELS; i++) {
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#endif
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#endif
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if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
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if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) {
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printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
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printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
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@ -438,7 +438,7 @@ void blackfin_dma_resume(void)
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#ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */
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#ifdef CONFIG_BF561 /* IMDMA channels doesn't have a PERIPHERAL_MAP */
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for (i = 0; i <= CH_MEM_STREAM3_SRC; i++)
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for (i = 0; i <= CH_MEM_STREAM3_SRC; i++)
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#else
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#else
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for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++)
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for (i = 0; i < MAX_DMA_CHANNELS; i++)
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#endif
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#endif
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dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
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dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
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}
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}
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@ -31,7 +31,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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@ -32,7 +32,7 @@
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#ifndef _MACH_DMA_H_
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define MAX_BLACKFIN_DMA_CHANNEL 16
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#define MAX_DMA_CHANNELS 16
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#define CH_PPI 0 /* PPI receive/transmit */
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#define CH_PPI 0 /* PPI receive/transmit */
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#define CH_EMAC_RX 1 /* Ethernet MAC receive */
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#define CH_EMAC_RX 1 /* Ethernet MAC receive */
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@ -31,7 +31,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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@ -32,7 +32,7 @@
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#ifndef _MACH_DMA_H_
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define MAX_BLACKFIN_DMA_CHANNEL 16
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#define MAX_DMA_CHANNELS 16
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#define CH_PPI 0 /* PPI receive/transmit or NFC */
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#define CH_PPI 0 /* PPI receive/transmit or NFC */
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#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
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#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
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@ -31,7 +31,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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@ -36,7 +36,7 @@
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#ifndef _MACH_DMA_H_
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define MAX_BLACKFIN_DMA_CHANNEL 12
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#define MAX_DMA_CHANNELS 12
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#define CH_PPI 0
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#define CH_PPI 0
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#define CH_SPORT0_RX 1
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#define CH_SPORT0_RX 1
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@ -31,7 +31,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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@ -32,7 +32,7 @@
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#ifndef _MACH_DMA_H_
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define MAX_BLACKFIN_DMA_CHANNEL 16
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#define MAX_DMA_CHANNELS 16
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#define CH_PPI 0
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#define CH_PPI 0
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#define CH_EMAC_RX 1
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#define CH_EMAC_RX 1
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@ -31,7 +31,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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@ -60,6 +60,6 @@
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#define CH_MEM_STREAM3_DEST 26
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#define CH_MEM_STREAM3_DEST 26
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#define CH_MEM_STREAM3_SRC 27
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#define CH_MEM_STREAM3_SRC 27
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#define MAX_BLACKFIN_DMA_CHANNEL 28
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#define MAX_DMA_CHANNELS 28
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#endif
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#endif
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@ -32,7 +32,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_NEXT_DESC_PTR,
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@ -71,6 +71,6 @@
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#define CH_MEM_STREAM3_DEST 30
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#define CH_MEM_STREAM3_DEST 30
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#define CH_MEM_STREAM3_SRC 31
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#define CH_MEM_STREAM3_SRC 31
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#define MAX_BLACKFIN_DMA_CHANNEL 32
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#define MAX_DMA_CHANNELS 32
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#endif
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#endif
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@ -31,7 +31,7 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/dma.h>
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struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
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(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
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@ -7,7 +7,7 @@
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#ifndef _MACH_DMA_H_
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define MAX_BLACKFIN_DMA_CHANNEL 36
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#define MAX_DMA_CHANNELS 36
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#define CH_PPI0 0
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#define CH_PPI0 0
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#define CH_PPI (CH_PPI0)
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#define CH_PPI (CH_PPI0)
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@ -32,7 +32,7 @@ void init_clocks(void)
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* For example, any automatic DMAs left by U-Boot for splash screens.
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* For example, any automatic DMAs left by U-Boot for splash screens.
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*/
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*/
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size_t i;
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size_t i;
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for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; ++i) {
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for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
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struct dma_register *dma = dma_io_base_addr[i];
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struct dma_register *dma = dma_io_base_addr[i];
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dma->cfg = 0;
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dma->cfg = 0;
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}
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}
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