dt-bindings: mtd: Add YAML schemas for the generic NAND options
The NAND chips in MTD have a bunch of generic options that are needed in a device tree. Add a YAML schemas for those. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>hifive-unleashed-5.2
Maxime Ripard
Miquel Raynal
parent
cf3bbe67be
commit
212e496935
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NAND Chip and NAND Controller Generic Binding
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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- Richard Weinberger <richard@nod.at>
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description: |
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The NAND controller should be represented with its own DT node, and
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all NAND chips attached to this controller should be defined as
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children nodes of the NAND controller. This representation should be
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enforced even for simple controllers supporting only one chip.
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The ECC strength and ECC step size properties define the user
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desires in terms of correction capability of a controller. Together,
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they request the ECC engine to correct {strength} bit errors per
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{size} bytes.
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The interpretation of these parameters is implementation-defined, so
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not all implementations must support all possible
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combinations. However, implementations are encouraged to further
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specify the value(s) they support.
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properties:
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$nodename:
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pattern: "^nand-controller(@.*)?"
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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ranges: true
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patternProperties:
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"^nand@[a-f0-9]$":
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properties:
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reg:
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description:
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Contains the native Ready/Busy IDs.
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nand-ecc-mode:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string
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- enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
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description:
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Desired ECC engine, either hardware (most of the time
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embedded in the NAND controller) or software correction
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(Linux will handle the calculations). soft_bch is deprecated
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and should be replaced by soft and nand-ecc-algo.
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nand-ecc-algo:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string
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- enum: [ hamming, bch, rs ]
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description:
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Desired ECC algorithm.
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nand-bus-width:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- enum: [ 8, 16 ]
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- default: 8
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description:
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Bus width to the NAND chip
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nand-on-flash-bbt:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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With this property, the OS will search the device for a Bad
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Block Table (BBT). If not found, it will create one, reserve
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a few blocks at the end of the device to store it and update
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it as the device ages. Otherwise, the out-of-band area of a
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few pages of all the blocks will be scanned at boot time to
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find Bad Block Markers (BBM). These markers will help to
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build a volatile BBT in RAM.
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nand-ecc-strength:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 1
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description:
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Maximum number of bits that can be corrected per ECC step.
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nand-ecc-step-size:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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- minimum: 1
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description:
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Number of data bytes covered by a single ECC step.
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nand-ecc-maximize:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Whether or not the ECC strength should be maximized. The
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maximum ECC strength is both controller and chip
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dependent. The ECC engine has to select the ECC config
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providing the best strength and taking the OOB area size
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constraint into account. This is particularly useful when
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only the in-band area is used by the upper layers, and you
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want to make your NAND as reliable as possible.
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nand-is-boot-medium:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Whether or not the NAND chip is a boot medium. Drivers might
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use this information to select ECC algorithms supported by
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the boot ROM or similar restrictions.
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nand-rb:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Contains the native Ready/Busy IDs.
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required:
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- reg
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required:
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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nand-controller {
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#address-cells = <1>;
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#size-cells = <0>;
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/* controller specific properties */
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nand@0 {
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reg = <0>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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/* controller specific properties */
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};
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};
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@ -1,75 +0,0 @@
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* NAND chip and NAND controller generic binding
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NAND controller/NAND chip representation:
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The NAND controller should be represented with its own DT node, and all
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NAND chips attached to this controller should be defined as children nodes
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of the NAND controller. This representation should be enforced even for
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simple controllers supporting only one chip.
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Mandatory NAND controller properties:
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- #address-cells: depends on your controller. Should at least be 1 to
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encode the CS line id.
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- #size-cells: depends on your controller. Put zero unless you need a
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mapping between CS lines and dedicated memory regions
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Optional NAND controller properties
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- ranges: only needed if you need to define a mapping between CS lines and
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memory regions
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Optional NAND chip properties:
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- nand-ecc-mode : String, operation mode of the NAND ecc mode.
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Supported values are: "none", "soft", "hw", "hw_syndrome",
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"hw_oob_first", "on-die".
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Deprecated values:
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"soft_bch": use "soft" and nand-ecc-algo instead
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- nand-ecc-algo: string, algorithm of NAND ECC.
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Valid values are: "hamming", "bch", "rs".
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- nand-bus-width : 8 or 16 bus width if not present 8
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- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
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- nand-ecc-strength: integer representing the number of bits to correct
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per ECC step.
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- nand-ecc-step-size: integer representing the number of data bytes
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that are covered by a single ECC step.
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- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
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strength. The maximum ECC strength is both controller and
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chip dependent. The controller side has to select the ECC
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config providing the best strength and taking the OOB area
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size constraint into account.
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This is particularly useful when only the in-band area is
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used by the upper layers, and you want to make your NAND
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as reliable as possible.
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- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use
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this information to select ECC algorithms supported by
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the boot ROM or similar restrictions.
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- nand-rb: shall contain the native Ready/Busy ids.
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The ECC strength and ECC step size properties define the correction capability
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of a controller. Together, they say a controller can correct "{strength} bit
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errors per {size} bytes".
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The interpretation of these parameters is implementation-defined, so not all
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implementations must support all possible combinations. However, implementations
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are encouraged to further specify the value(s) they support.
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Example:
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nand-controller {
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#address-cells = <1>;
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#size-cells = <0>;
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/* controller specific properties */
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nand@0 {
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reg = <0>;
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nand-ecc-mode = "soft";
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nand-ecc-algo = "bch";
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/* controller specific properties */
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};
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};
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