[SCSI] ipr: add support for multiple stages of initialization
This patch adds support for using the new IOA initialization feedback register. It also enables 64 bit support in the ipr_ioafp_identify_hrrq and ipr_mask_and_clear_interrupts routines. Signed-off-by: Wayne Boyer <wayneb@linux.vnet.ibm.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>hifive-unleashed-5.1
Wayne Boyer
James Bottomley
parent
f72919ec2b
commit
214777ba12
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@ -106,13 +106,20 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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{
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.set_interrupt_mask_reg = 0x0022C,
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.clr_interrupt_mask_reg = 0x00230,
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.clr_interrupt_mask_reg32 = 0x00230,
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.sense_interrupt_mask_reg = 0x0022C,
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.sense_interrupt_mask_reg32 = 0x0022C,
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.clr_interrupt_reg = 0x00228,
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.clr_interrupt_reg32 = 0x00228,
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.sense_interrupt_reg = 0x00224,
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.sense_interrupt_reg32 = 0x00224,
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.ioarrin_reg = 0x00404,
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.sense_uproc_interrupt_reg = 0x00214,
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.sense_uproc_interrupt_reg32 = 0x00214,
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.set_uproc_interrupt_reg = 0x00214,
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.clr_uproc_interrupt_reg = 0x00218
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.set_uproc_interrupt_reg32 = 0x00214,
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.clr_uproc_interrupt_reg = 0x00218,
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.clr_uproc_interrupt_reg32 = 0x00218
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}
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},
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{ /* Snipe and Scamp */
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@ -121,13 +128,20 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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{
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.set_interrupt_mask_reg = 0x00288,
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.clr_interrupt_mask_reg = 0x0028C,
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.clr_interrupt_mask_reg32 = 0x0028C,
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.sense_interrupt_mask_reg = 0x00288,
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.sense_interrupt_mask_reg32 = 0x00288,
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.clr_interrupt_reg = 0x00284,
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.clr_interrupt_reg32 = 0x00284,
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.sense_interrupt_reg = 0x00280,
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.sense_interrupt_reg32 = 0x00280,
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.ioarrin_reg = 0x00504,
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.sense_uproc_interrupt_reg = 0x00290,
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.sense_uproc_interrupt_reg32 = 0x00290,
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.set_uproc_interrupt_reg = 0x00290,
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.clr_uproc_interrupt_reg = 0x00294
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.set_uproc_interrupt_reg32 = 0x00290,
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.clr_uproc_interrupt_reg = 0x00294,
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.clr_uproc_interrupt_reg32 = 0x00294
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}
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},
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{ /* CRoC */
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@ -136,13 +150,21 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
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{
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.set_interrupt_mask_reg = 0x00010,
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.clr_interrupt_mask_reg = 0x00018,
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.clr_interrupt_mask_reg32 = 0x0001C,
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.sense_interrupt_mask_reg = 0x00010,
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.sense_interrupt_mask_reg32 = 0x00014,
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.clr_interrupt_reg = 0x00008,
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.clr_interrupt_reg32 = 0x0000C,
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.sense_interrupt_reg = 0x00000,
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.sense_interrupt_reg32 = 0x00004,
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.ioarrin_reg = 0x00070,
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.sense_uproc_interrupt_reg = 0x00020,
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.sense_uproc_interrupt_reg32 = 0x00024,
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.set_uproc_interrupt_reg = 0x00020,
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.set_uproc_interrupt_reg32 = 0x00024,
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.clr_uproc_interrupt_reg = 0x00028,
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.clr_uproc_interrupt_reg32 = 0x0002C,
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.init_feedback_reg = 0x0005C,
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.dump_addr_reg = 0x00064,
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.dump_data_reg = 0x00068
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}
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@ -592,10 +614,15 @@ static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
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ioa_cfg->allow_interrupts = 0;
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/* Set interrupt mask to stop all new interrupts */
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writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
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if (ioa_cfg->sis64)
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writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
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else
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writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
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/* Clear any pending interrupts */
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writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg);
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if (ioa_cfg->sis64)
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writel(~0, ioa_cfg->regs.clr_interrupt_reg);
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writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
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}
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@ -2561,7 +2588,7 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
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/* Write IOA interrupt reg starting LDUMP state */
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writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
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ioa_cfg->regs.set_uproc_interrupt_reg);
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ioa_cfg->regs.set_uproc_interrupt_reg32);
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/* Wait for IO debug acknowledge */
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if (ipr_wait_iodbg_ack(ioa_cfg,
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@ -2580,7 +2607,7 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
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/* Signal address valid - clear IOA Reset alert */
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writel(IPR_UPROCI_RESET_ALERT,
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ioa_cfg->regs.clr_uproc_interrupt_reg);
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ioa_cfg->regs.clr_uproc_interrupt_reg32);
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for (i = 0; i < length_in_words; i++) {
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/* Wait for IO debug acknowledge */
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@ -2605,10 +2632,10 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
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/* Signal end of block transfer. Set reset alert then clear IO debug ack */
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writel(IPR_UPROCI_RESET_ALERT,
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ioa_cfg->regs.set_uproc_interrupt_reg);
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ioa_cfg->regs.set_uproc_interrupt_reg32);
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writel(IPR_UPROCI_IO_DEBUG_ALERT,
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ioa_cfg->regs.clr_uproc_interrupt_reg);
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ioa_cfg->regs.clr_uproc_interrupt_reg32);
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/* Signal dump data received - Clear IO debug Ack */
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writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
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@ -2617,7 +2644,7 @@ static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
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/* Wait for IOA to signal LDUMP exit - IOA reset alert will be cleared */
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while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
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temp_pcii_reg =
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readl(ioa_cfg->regs.sense_uproc_interrupt_reg);
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readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
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if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
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return 0;
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@ -4831,11 +4858,29 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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return IRQ_NONE;
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}
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int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg;
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/* If an interrupt on the adapter did not occur, ignore it */
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/* If an interrupt on the adapter did not occur, ignore it.
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* Or in the case of SIS 64, check for a stage change interrupt.
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*/
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if (unlikely((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0)) {
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if (ioa_cfg->sis64) {
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int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
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/* clear stage change */
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writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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list_del(&ioa_cfg->reset_cmd->queue);
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del_timer(&ioa_cfg->reset_cmd->timer);
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ipr_reset_ioa_job(ioa_cfg->reset_cmd);
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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return IRQ_HANDLED;
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}
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}
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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return IRQ_NONE;
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}
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@ -4878,8 +4923,8 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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if (ipr_cmd != NULL) {
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/* Clear the PCI interrupt */
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do {
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writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg;
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} while (int_reg & IPR_PCII_HRRQ_UPDATED &&
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num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
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@ -6887,7 +6932,7 @@ static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
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}
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/**
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* ipr_ioafp_indentify_hrrq - Send Identify Host RRQ.
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* ipr_ioafp_identify_hrrq - Send Identify Host RRQ.
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* @ipr_cmd: ipr command struct
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*
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* This function send an Identify Host Request Response Queue
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@ -6896,7 +6941,7 @@ static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
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* Return value:
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* IPR_RC_JOB_RETURN
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**/
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static int ipr_ioafp_indentify_hrrq(struct ipr_cmnd *ipr_cmd)
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static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
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{
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struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
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struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
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@ -6908,19 +6953,32 @@ static int ipr_ioafp_indentify_hrrq(struct ipr_cmnd *ipr_cmd)
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ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
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ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
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if (ioa_cfg->sis64)
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ioarcb->cmd_pkt.cdb[1] = 0x1;
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ioarcb->cmd_pkt.cdb[2] =
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((u32) ioa_cfg->host_rrq_dma >> 24) & 0xff;
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((u64) ioa_cfg->host_rrq_dma >> 24) & 0xff;
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ioarcb->cmd_pkt.cdb[3] =
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((u32) ioa_cfg->host_rrq_dma >> 16) & 0xff;
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((u64) ioa_cfg->host_rrq_dma >> 16) & 0xff;
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ioarcb->cmd_pkt.cdb[4] =
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((u32) ioa_cfg->host_rrq_dma >> 8) & 0xff;
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((u64) ioa_cfg->host_rrq_dma >> 8) & 0xff;
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ioarcb->cmd_pkt.cdb[5] =
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((u32) ioa_cfg->host_rrq_dma) & 0xff;
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((u64) ioa_cfg->host_rrq_dma) & 0xff;
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ioarcb->cmd_pkt.cdb[7] =
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((sizeof(u32) * IPR_NUM_CMD_BLKS) >> 8) & 0xff;
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ioarcb->cmd_pkt.cdb[8] =
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(sizeof(u32) * IPR_NUM_CMD_BLKS) & 0xff;
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if (ioa_cfg->sis64) {
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ioarcb->cmd_pkt.cdb[10] =
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((u64) ioa_cfg->host_rrq_dma >> 56) & 0xff;
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ioarcb->cmd_pkt.cdb[11] =
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((u64) ioa_cfg->host_rrq_dma >> 48) & 0xff;
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ioarcb->cmd_pkt.cdb[12] =
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((u64) ioa_cfg->host_rrq_dma >> 40) & 0xff;
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ioarcb->cmd_pkt.cdb[13] =
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((u64) ioa_cfg->host_rrq_dma >> 32) & 0xff;
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}
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ipr_cmd->job_step = ipr_ioafp_std_inquiry;
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ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
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@ -7004,6 +7062,57 @@ static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
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memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
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}
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/**
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* ipr_reset_next_stage - Process IPL stage change based on feedback register.
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* @ipr_cmd: ipr command struct
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*
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* Return value:
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* IPR_RC_JOB_CONTINUE / IPR_RC_JOB_RETURN
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**/
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static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
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{
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unsigned long stage, stage_time;
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u32 feedback;
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volatile u32 int_reg;
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struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
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u64 maskval = 0;
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feedback = readl(ioa_cfg->regs.init_feedback_reg);
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stage = feedback & IPR_IPL_INIT_STAGE_MASK;
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stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
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ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
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/* sanity check the stage_time value */
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if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
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stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
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else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
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stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
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if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
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writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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stage_time = ioa_cfg->transop_timeout;
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ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
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} else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
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ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
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maskval = IPR_PCII_IPL_STAGE_CHANGE;
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maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
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writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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return IPR_RC_JOB_CONTINUE;
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}
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ipr_cmd->timer.data = (unsigned long) ipr_cmd;
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ipr_cmd->timer.expires = jiffies + stage_time * HZ;
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ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
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ipr_cmd->done = ipr_reset_ioa_job;
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add_timer(&ipr_cmd->timer);
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list_add_tail(&ipr_cmd->queue, &ioa_cfg->pending_q);
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return IPR_RC_JOB_RETURN;
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}
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/**
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* ipr_reset_enable_ioa - Enable the IOA following a reset.
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* @ipr_cmd: ipr command struct
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@ -7020,7 +7129,7 @@ static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
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volatile u32 int_reg;
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ENTER;
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ipr_cmd->job_step = ipr_ioafp_indentify_hrrq;
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ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
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ipr_init_ioa_mem(ioa_cfg);
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ioa_cfg->allow_interrupts = 1;
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@ -7028,19 +7137,27 @@ static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
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if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
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writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
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ioa_cfg->regs.clr_interrupt_mask_reg);
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ioa_cfg->regs.clr_interrupt_mask_reg32);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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return IPR_RC_JOB_CONTINUE;
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}
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/* Enable destructive diagnostics on IOA */
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writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg);
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writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
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writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
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if (ioa_cfg->sis64)
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writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_mask_reg);
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writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg);
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int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
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if (ioa_cfg->sis64) {
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ipr_cmd->job_step = ipr_reset_next_stage;
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return IPR_RC_JOB_CONTINUE;
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}
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ipr_cmd->timer.data = (unsigned long) ipr_cmd;
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ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
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ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
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@ -7374,7 +7491,7 @@ static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
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if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
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ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
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writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg);
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writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
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ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
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} else {
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ipr_cmd->job_step = ioa_cfg->reset;
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@ -8104,15 +8221,23 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
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t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
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t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
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t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
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t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
|
||||
t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
|
||||
t->clr_interrupt_reg = base + p->clr_interrupt_reg;
|
||||
t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
|
||||
t->sense_interrupt_reg = base + p->sense_interrupt_reg;
|
||||
t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
|
||||
t->ioarrin_reg = base + p->ioarrin_reg;
|
||||
t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
|
||||
t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
|
||||
t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
|
||||
t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
|
||||
t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
|
||||
t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
|
||||
|
||||
if (ioa_cfg->sis64) {
|
||||
t->init_feedback_reg = base + p->init_feedback_reg;
|
||||
t->dump_addr_reg = base + p->dump_addr_reg;
|
||||
t->dump_data_reg = base + p->dump_data_reg;
|
||||
}
|
||||
|
|
@ -8187,7 +8312,7 @@ static int __devinit ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg,
|
|||
init_waitqueue_head(&ioa_cfg->msi_wait_q);
|
||||
ioa_cfg->msi_received = 0;
|
||||
ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
|
||||
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg);
|
||||
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
|
||||
int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
|
||||
spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
|
||||
|
||||
|
|
@ -8198,7 +8323,7 @@ static int __devinit ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg,
|
|||
} else if (ipr_debug)
|
||||
dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq);
|
||||
|
||||
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg);
|
||||
writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
|
||||
int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
|
||||
wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
|
||||
ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
|
||||
|
|
@ -8378,9 +8503,9 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev,
|
|||
* If HRRQ updated interrupt is not masked, or reset alert is set,
|
||||
* the card is in an unknown state and needs a hard reset
|
||||
*/
|
||||
mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
|
||||
interrupts = readl(ioa_cfg->regs.sense_interrupt_reg);
|
||||
uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg);
|
||||
mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
|
||||
interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
|
||||
uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
|
||||
if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
|
||||
ioa_cfg->needs_hard_reset = 1;
|
||||
if (interrupts & IPR_PCII_ERROR_INTERRUPTS)
|
||||
|
|
|
|||
|
|
@ -232,6 +232,13 @@
|
|||
#define IPR_DOORBELL 0x82800000
|
||||
#define IPR_RUNTIME_RESET 0x40000000
|
||||
|
||||
#define IPR_IPL_INIT_MIN_STAGE_TIME 5
|
||||
#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
|
||||
#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
|
||||
#define IPR_IPL_INIT_STAGE_MASK 0xff000000
|
||||
#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
|
||||
#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
|
||||
|
||||
#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
|
||||
#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
|
||||
#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
|
||||
|
|
@ -1196,14 +1203,23 @@ struct ipr_misc_cbs {
|
|||
struct ipr_interrupt_offsets {
|
||||
unsigned long set_interrupt_mask_reg;
|
||||
unsigned long clr_interrupt_mask_reg;
|
||||
unsigned long clr_interrupt_mask_reg32;
|
||||
unsigned long sense_interrupt_mask_reg;
|
||||
unsigned long sense_interrupt_mask_reg32;
|
||||
unsigned long clr_interrupt_reg;
|
||||
unsigned long clr_interrupt_reg32;
|
||||
|
||||
unsigned long sense_interrupt_reg;
|
||||
unsigned long sense_interrupt_reg32;
|
||||
unsigned long ioarrin_reg;
|
||||
unsigned long sense_uproc_interrupt_reg;
|
||||
unsigned long sense_uproc_interrupt_reg32;
|
||||
unsigned long set_uproc_interrupt_reg;
|
||||
unsigned long set_uproc_interrupt_reg32;
|
||||
unsigned long clr_uproc_interrupt_reg;
|
||||
unsigned long clr_uproc_interrupt_reg32;
|
||||
|
||||
unsigned long init_feedback_reg;
|
||||
|
||||
unsigned long dump_addr_reg;
|
||||
unsigned long dump_data_reg;
|
||||
|
|
@ -1212,14 +1228,23 @@ struct ipr_interrupt_offsets {
|
|||
struct ipr_interrupts {
|
||||
void __iomem *set_interrupt_mask_reg;
|
||||
void __iomem *clr_interrupt_mask_reg;
|
||||
void __iomem *clr_interrupt_mask_reg32;
|
||||
void __iomem *sense_interrupt_mask_reg;
|
||||
void __iomem *sense_interrupt_mask_reg32;
|
||||
void __iomem *clr_interrupt_reg;
|
||||
void __iomem *clr_interrupt_reg32;
|
||||
|
||||
void __iomem *sense_interrupt_reg;
|
||||
void __iomem *sense_interrupt_reg32;
|
||||
void __iomem *ioarrin_reg;
|
||||
void __iomem *sense_uproc_interrupt_reg;
|
||||
void __iomem *sense_uproc_interrupt_reg32;
|
||||
void __iomem *set_uproc_interrupt_reg;
|
||||
void __iomem *set_uproc_interrupt_reg32;
|
||||
void __iomem *clr_uproc_interrupt_reg;
|
||||
void __iomem *clr_uproc_interrupt_reg32;
|
||||
|
||||
void __iomem *init_feedback_reg;
|
||||
|
||||
void __iomem *dump_addr_reg;
|
||||
void __iomem *dump_data_reg;
|
||||
|
|
|
|||
Loading…
Reference in New Issue