MIPS: lantiq: Fix Danube USB clock
On Danube the USB0 controller registers are at 1e101000 and the USB0 PHY register is athifive-unleashed-5.11f203018
similar to all other lantiq SoCs. Activate the USB controller gating clock thorough the USB controller driver and not the PHY. This fixes a problem introduced in a previous commit. Fixes:dea54fbad3
("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module") Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.14+ Patchwork: https://patchwork.linux-mips.org/patch/18816/ Signed-off-by: James Hogan <jhogan@kernel.org>
parent
0c8efd610b
commit
214cbc1473
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@ -560,7 +560,7 @@ void __init ltq_soc_init(void)
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
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clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
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clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
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clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
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clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
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clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
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