[MIPS] c-r3k: Implement flush_cache_range()
Contrary to the belief of some, the R3000 and related processors did have caches, both a data and an instruction cache. Here is an implementation of r3k_flush_cache_page(), which is the processor-specific back-end for flush_cache_range(), done according to the spec in Documentation/cachetlb.txt. While at it, remove an unused local function: get_phys_page(), do some trivial formatting fixes and modernise debugging facilities. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -7,7 +7,7 @@
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* Tx39XX R4k style caches added. HK
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* Copyright (C) 1998, 1999, 2000 Harald Koerfgen
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* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
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* Copyright (C) 2001, 2004 Maciej W. Rozycki
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* Copyright (C) 2001, 2004, 2007 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -26,8 +26,6 @@
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static unsigned long icache_size, dcache_size; /* Size in bytes */
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static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */
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#undef DEBUG_CACHE
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unsigned long __init r3k_cache_size(unsigned long ca_flags)
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{
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unsigned long flags, status, dummy, size;
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@ -217,26 +215,6 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
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write_c0_status(flags);
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}
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static inline unsigned long get_phys_page(unsigned long addr,
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struct mm_struct *mm)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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unsigned long physpage;
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pgd = pgd_offset(mm, addr);
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pud = pud_offset(pgd, addr);
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pmd = pmd_offset(pud, addr);
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pte = pte_offset(pmd, addr);
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if ((physpage = pte_val(*pte)) & _PAGE_VALID)
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return KSEG0ADDR(physpage & PAGE_MASK);
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return 0;
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}
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static inline void r3k_flush_cache_all(void)
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{
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}
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@ -252,12 +230,40 @@ static void r3k_flush_cache_mm(struct mm_struct *mm)
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}
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static void r3k_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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unsigned long start, unsigned long end)
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{
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}
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static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
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static void r3k_flush_cache_page(struct vm_area_struct *vma,
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unsigned long addr, unsigned long pfn)
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{
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unsigned long kaddr = KSEG0ADDR(pfn << PAGE_SHIFT);
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int exec = vma->vm_flags & VM_EXEC;
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struct mm_struct *mm = vma->vm_mm;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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pr_debug("cpage[%08lx,%08lx]\n",
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cpu_context(smp_processor_id(), mm), addr);
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/* No ASID => no such page in the cache. */
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if (cpu_context(smp_processor_id(), mm) == 0)
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return;
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pgdp = pgd_offset(mm, addr);
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pudp = pud_offset(pgdp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset(pmdp, addr);
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/* Invalid => no such page in the cache. */
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if (!(pte_val(*ptep) & _PAGE_PRESENT))
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return;
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r3k_flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
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if (exec)
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r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE);
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}
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static void local_r3k_flush_data_cache_page(void *addr)
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@ -272,9 +278,7 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long flags;
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#ifdef DEBUG_CACHE
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printk("csigtramp[%08lx]", addr);
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#endif
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pr_debug("csigtramp[%08lx]\n", addr);
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flags = read_c0_status();
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