Blackfin: punt NFC MMR bits
Now that the NFC driver has its own defines, scrub the ones from the global namespace to avoid ugly collisions with common code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -1738,85 +1738,4 @@
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#define nAFEXIT 0x0
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#define SECSTAT 0xe0 /* Secure Status */
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/* Bit masks for NFC_CTL */
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#define WR_DLY 0xf /* Write Strobe Delay */
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#define RD_DLY 0xf0 /* Read Strobe Delay */
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#define NWIDTH 0x100 /* NAND Data Width */
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#define nNWIDTH 0x0
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#define PG_SIZE 0x200 /* Page Size */
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#define nPG_SIZE 0x0
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/* Bit masks for NFC_STAT */
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#define NBUSY 0x1 /* Not Busy */
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#define nNBUSY 0x0
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#define WB_FULL 0x2 /* Write Buffer Full */
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#define nWB_FULL 0x0
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#define PG_WR_STAT 0x4 /* Page Write Pending */
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#define nPG_WR_STAT 0x0
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#define PG_RD_STAT 0x8 /* Page Read Pending */
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#define nPG_RD_STAT 0x0
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#define WB_EMPTY 0x10 /* Write Buffer Empty */
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#define nWB_EMPTY 0x0
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/* Bit masks for NFC_IRQSTAT */
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#define NBUSYIRQ 0x1 /* Not Busy IRQ */
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#define nNBUSYIRQ 0x0
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#define WB_OVF 0x2 /* Write Buffer Overflow */
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#define nWB_OVF 0x0
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#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
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#define nWB_EDGE 0x0
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#define RD_RDY 0x8 /* Read Data Ready */
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#define nRD_RDY 0x0
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#define WR_DONE 0x10 /* Page Write Done */
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#define nWR_DONE 0x0
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/* Bit masks for NFC_IRQMASK */
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#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
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#define nMASK_BUSYIRQ 0x0
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#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
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#define nMASK_WBOVF 0x0
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#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
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#define nMASK_WBEMPTY 0x0
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#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
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#define nMASK_RDRDY 0x0
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#define MASK_WRDONE 0x10 /* Mask Write Done */
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#define nMASK_WRDONE 0x0
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/* Bit masks for NFC_RST */
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#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
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#define nECC_RST 0x0
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/* Bit masks for NFC_PGCTL */
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#define PG_RD_START 0x1 /* Page Read Start */
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#define nPG_RD_START 0x0
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#define PG_WR_START 0x2 /* Page Write Start */
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#define nPG_WR_START 0x0
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/* Bit masks for NFC_ECC0 */
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#define ECC0 0x7ff /* Parity Calculation Result0 */
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/* Bit masks for NFC_ECC1 */
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#define ECC1 0x7ff /* Parity Calculation Result1 */
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/* Bit masks for NFC_ECC2 */
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#define ECC2 0x7ff /* Parity Calculation Result2 */
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/* Bit masks for NFC_ECC3 */
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#define ECC3 0x7ff /* Parity Calculation Result3 */
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/* Bit masks for NFC_COUNT */
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#define ECCCNT 0x3ff /* Transfer Count */
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#endif /* _DEF_BF52X_H */
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@ -2044,66 +2044,6 @@
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#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
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#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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/* Bit masks for NFC_CTL */
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#define WR_DLY 0xf /* Write Strobe Delay */
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#define RD_DLY 0xf0 /* Read Strobe Delay */
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#define NWIDTH 0x100 /* NAND Data Width */
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#define PG_SIZE 0x200 /* Page Size */
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/* Bit masks for NFC_STAT */
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#define NBUSY 0x1 /* Not Busy */
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#define WB_FULL 0x2 /* Write Buffer Full */
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#define PG_WR_STAT 0x4 /* Page Write Pending */
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#define PG_RD_STAT 0x8 /* Page Read Pending */
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#define WB_EMPTY 0x10 /* Write Buffer Empty */
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/* Bit masks for NFC_IRQSTAT */
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#define NBUSYIRQ 0x1 /* Not Busy IRQ */
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#define WB_OVF 0x2 /* Write Buffer Overflow */
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#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
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#define RD_RDY 0x8 /* Read Data Ready */
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#define WR_DONE 0x10 /* Page Write Done */
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/* Bit masks for NFC_IRQMASK */
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#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
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#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
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#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
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#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
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#define MASK_WRDONE 0x10 /* Mask Write Done */
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/* Bit masks for NFC_RST */
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#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
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/* Bit masks for NFC_PGCTL */
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#define PG_RD_START 0x1 /* Page Read Start */
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#define PG_WR_START 0x2 /* Page Write Start */
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/* Bit masks for NFC_ECC0 */
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#define ECC0 0x7ff /* Parity Calculation Result0 */
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/* Bit masks for NFC_ECC1 */
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#define ECC1 0x7ff /* Parity Calculation Result1 */
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/* Bit masks for NFC_ECC2 */
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#define ECC2 0x7ff /* Parity Calculation Result2 */
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/* Bit masks for NFC_ECC3 */
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#define ECC3 0x7ff /* Parity Calculation Result3 */
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/* Bit masks for NFC_COUNT */
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#define ECCCNT 0x3ff /* Transfer Count */
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/* Bit masks for EPPIx_STATUS */
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#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
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