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coresight: remove the unnecessary configuration coresight-default-sink 

The coresight-default-sink configuration option has been
removed from the framework. As such remove it from DT and bindings.

Signed-off-by: Kaixu Xia <xiakaixu@huawei.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.1
Kaixu Xia 2015-03-30 14:13:39 -06:00 committed by Greg Kroah-Hartman
parent a0a500efab
commit 223437c72a
5 changed files with 0 additions and 5 deletions
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1
Documentation/devicetree/bindings/arm/coresight.txt
View File

@ -61,7 +61,6 @@ Example:
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
coresight-default-sink;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
port {

1
arch/arm/boot/dts/hip04.dtsi
View File

@ -275,7 +275,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3c42000 0 0x1000>;
coresight-default-sink;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {

1
arch/arm/boot/dts/omap3-beagle-xm.dts
View File

@ -150,7 +150,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x5401b000 0x1000>;
coresight-default-sink;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {

1
arch/arm/boot/dts/omap3-beagle.dts
View File

@ -145,7 +145,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x5401b000 0x1000>;
coresight-default-sink;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {

1
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View File

@ -362,7 +362,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
coresight-default-sink;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
port {