clk: qcom: Add support for banked MD RCGs
The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>hifive-unleashed-5.1
Stephen Boyd
parent
ae3669ac5c
commit
229fd4a505
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@ -68,16 +68,16 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
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{
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struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 ns, ctl;
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u32 ns, reg;
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int bank;
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int i;
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struct src_sel *s;
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regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
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bank = reg_to_bank(rcg, ctl);
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regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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bank = reg_to_bank(rcg, reg);
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s = &rcg->s[bank];
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regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
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regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
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ns = ns_to_src(s, ns);
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for (i = 0; i < num_parents; i++)
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@ -193,90 +193,93 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
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static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
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{
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u32 ns, md, ctl, *regp;
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u32 ns, md, reg;
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int bank, new_bank;
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struct mn *mn;
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struct pre_div *p;
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struct src_sel *s;
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bool enabled;
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u32 md_reg;
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u32 bank_reg;
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u32 md_reg, ns_reg;
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bool banked_mn = !!rcg->mn[1].width;
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bool banked_p = !!rcg->p[1].pre_div_width;
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struct clk_hw *hw = &rcg->clkr.hw;
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enabled = __clk_is_enabled(hw->clk);
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regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
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regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
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if (banked_mn) {
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regp = &ctl;
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bank_reg = rcg->clkr.enable_reg;
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} else {
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regp = &ns;
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bank_reg = rcg->ns_reg;
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}
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bank = reg_to_bank(rcg, *regp);
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regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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bank = reg_to_bank(rcg, reg);
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new_bank = enabled ? !bank : bank;
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ns_reg = rcg->ns_reg[new_bank];
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regmap_read(rcg->clkr.regmap, ns_reg, &ns);
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if (banked_mn) {
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mn = &rcg->mn[new_bank];
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md_reg = rcg->md_reg[new_bank];
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ns |= BIT(mn->mnctr_reset_bit);
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regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
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regmap_write(rcg->clkr.regmap, ns_reg, ns);
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regmap_read(rcg->clkr.regmap, md_reg, &md);
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md = mn_to_md(mn, f->m, f->n, md);
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regmap_write(rcg->clkr.regmap, md_reg, md);
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ns = mn_to_ns(mn, f->m, f->n, ns);
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regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
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regmap_write(rcg->clkr.regmap, ns_reg, ns);
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ctl = mn_to_reg(mn, f->m, f->n, ctl);
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regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
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/* Two NS registers means mode control is in NS register */
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if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
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ns = mn_to_reg(mn, f->m, f->n, ns);
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regmap_write(rcg->clkr.regmap, ns_reg, ns);
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} else {
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reg = mn_to_reg(mn, f->m, f->n, reg);
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regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
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}
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ns &= ~BIT(mn->mnctr_reset_bit);
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regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
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} else {
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regmap_write(rcg->clkr.regmap, ns_reg, ns);
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}
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if (banked_p) {
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p = &rcg->p[new_bank];
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ns = pre_div_to_ns(p, f->pre_div - 1, ns);
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}
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s = &rcg->s[new_bank];
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ns = src_to_ns(s, s->parent_map[f->src], ns);
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regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
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regmap_write(rcg->clkr.regmap, ns_reg, ns);
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if (enabled) {
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*regp ^= BIT(rcg->mux_sel_bit);
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regmap_write(rcg->clkr.regmap, bank_reg, *regp);
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regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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reg ^= BIT(rcg->mux_sel_bit);
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regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
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}
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}
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static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
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u32 ns, ctl, md, reg;
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u32 ns, md, reg;
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int bank;
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struct freq_tbl f = { 0 };
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bool banked_mn = !!rcg->mn[1].width;
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bool banked_p = !!rcg->p[1].pre_div_width;
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regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
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regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
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reg = banked_mn ? ctl : ns;
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regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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bank = reg_to_bank(rcg, reg);
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regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
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if (banked_mn) {
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regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
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f.m = md_to_m(&rcg->mn[bank], md);
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f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
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} else {
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f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
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}
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f.src = index;
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if (banked_p)
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f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
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f.src = index;
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configure_bank(rcg, &f);
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return 0;
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@ -337,28 +340,30 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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u32 m, n, pre_div, ns, md, mode, reg;
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int bank;
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struct mn *mn;
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bool banked_p = !!rcg->p[1].pre_div_width;
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bool banked_mn = !!rcg->mn[1].width;
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regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
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if (banked_mn)
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regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, ®);
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else
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reg = ns;
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regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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bank = reg_to_bank(rcg, reg);
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regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
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m = n = pre_div = mode = 0;
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if (banked_mn) {
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mn = &rcg->mn[bank];
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regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
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m = md_to_m(mn, md);
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n = ns_m_to_n(mn, ns, m);
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/* Two NS registers means mode control is in NS register */
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if (rcg->ns_reg[0] != rcg->ns_reg[1])
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reg = ns;
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mode = reg_to_mnctr_mode(mn, reg);
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return calc_rate(parent_rate, m, n, mode, 0);
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} else {
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pre_div = ns_to_pre_div(&rcg->p[bank], ns);
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return calc_rate(parent_rate, 0, 0, 0, pre_div);
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}
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if (banked_p)
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pre_div = ns_to_pre_div(&rcg->p[bank], ns);
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return calc_rate(parent_rate, m, n, mode, pre_div);
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}
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static long _freq_tbl_determine_rate(struct clk_hw *hw,
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@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
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* struct clk_dyn_rcg - root clock generator with glitch free mux
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*
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* @mux_sel_bit: bit to switch glitch free mux
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* @ns_reg: NS register
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* @ns_reg: NS0 and NS1 register
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* @md_reg: MD0 and MD1 register
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* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
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* @mn: mn counter (banked)
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* @s: source selector (banked)
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* @freq_tbl: frequency table
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@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
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*
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*/
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struct clk_dyn_rcg {
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u32 ns_reg;
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u32 ns_reg[2];
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u32 md_reg[2];
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u32 bank_reg;
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u8 mux_sel_bit;
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@ -773,9 +773,11 @@ static struct freq_tbl clk_tbl_gfx2d[] = {
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};
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static struct clk_dyn_rcg gfx2d0_src = {
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.ns_reg = 0x0070,
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.ns_reg[0] = 0x0070,
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.ns_reg[1] = 0x0070,
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.md_reg[0] = 0x0064,
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.md_reg[1] = 0x0068,
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.bank_reg = 0x0060,
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.mn[0] = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 25,
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@ -831,9 +833,11 @@ static struct clk_branch gfx2d0_clk = {
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};
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static struct clk_dyn_rcg gfx2d1_src = {
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.ns_reg = 0x007c,
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.ns_reg[0] = 0x007c,
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.ns_reg[1] = 0x007c,
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.md_reg[0] = 0x0078,
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.md_reg[1] = 0x006c,
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.bank_reg = 0x0074,
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.mn[0] = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 25,
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@ -930,9 +934,11 @@ static struct freq_tbl clk_tbl_gfx3d_8064[] = {
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};
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static struct clk_dyn_rcg gfx3d_src = {
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.ns_reg = 0x008c,
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.ns_reg[0] = 0x008c,
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.ns_reg[1] = 0x008c,
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.md_reg[0] = 0x0084,
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.md_reg[1] = 0x0088,
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.bank_reg = 0x0080,
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.mn[0] = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 25,
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@ -1006,9 +1012,11 @@ static struct freq_tbl clk_tbl_vcap[] = {
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};
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static struct clk_dyn_rcg vcap_src = {
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.ns_reg = 0x021c,
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.ns_reg[0] = 0x021c,
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.ns_reg[1] = 0x021c,
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.md_reg[0] = 0x01ec,
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.md_reg[1] = 0x0218,
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.bank_reg = 0x0178,
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.mn[0] = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 23,
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@ -1211,9 +1219,11 @@ static struct freq_tbl clk_tbl_mdp[] = {
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};
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static struct clk_dyn_rcg mdp_src = {
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.ns_reg = 0x00d0,
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.ns_reg[0] = 0x00d0,
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.ns_reg[1] = 0x00d0,
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.md_reg[0] = 0x00c4,
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.md_reg[1] = 0x00c8,
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.bank_reg = 0x00c0,
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.mn[0] = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 31,
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@ -1318,7 +1328,9 @@ static struct freq_tbl clk_tbl_rot[] = {
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};
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static struct clk_dyn_rcg rot_src = {
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.ns_reg = 0x00e8,
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.ns_reg[0] = 0x00e8,
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.ns_reg[1] = 0x00e8,
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.bank_reg = 0x00e8,
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.p[0] = {
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.pre_div_shift = 22,
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.pre_div_width = 4,
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@ -1542,9 +1554,11 @@ static struct freq_tbl clk_tbl_vcodec[] = {
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};
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static struct clk_dyn_rcg vcodec_src = {
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.ns_reg = 0x0100,
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.ns_reg[0] = 0x0100,
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.ns_reg[1] = 0x0100,
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.md_reg[0] = 0x00fc,
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.md_reg[1] = 0x0128,
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.bank_reg = 0x00f8,
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.mn[0] = {
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.mnctr_en_bit = 5,
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.mnctr_reset_bit = 31,
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