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First round of fixes for meson clocks targeted for v5.1: 

- g12a: Fix VPU clock parents and mux mask
 - gxbb: Add CLK_DIVIDER_ROUND_CLOSEST to video decoder clocks
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Merge tag 'meson-clk-fixes-for-5.1' of https://github.com/BayLibre/clk-meson into clk-fixes

Pull a round of fixes for meson clocks from Neil Armstrong:
 - g12a: Fix VPU clock parents and mux mask
 - gxbb: Add CLK_DIVIDER_ROUND_CLOSEST to video decoder clocks

* tag 'meson-clk-fixes-for-5.1' of https://github.com/BayLibre/clk-meson:
  clk: meson-g12a: fix VPU clock parents
  clk: meson: g12a: fix VPU clock muxes mask
  clk: meson-gxbb: round the vdec dividers to closest
hifive-unleashed-5.1
Stephen Boyd 2019-03-19 14:30:36 -07:00
parent 45b0668211 9e05e49c29
commit 22cf7c6f8e
2 changed files with 5 additions and 3 deletions
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6
drivers/clk/meson/g12a.c
View File

@ -960,14 +960,14 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = {
/* VPU Clock */
static const char * const g12a_vpu_parent_names[] = {
"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
"fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
"mpll1", "vid_pll", "hifi_pll", "gp0_pll",
};
static struct clk_regmap g12a_vpu_0_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 0x3,
.mask = 0x7,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
@ -1011,7 +1011,7 @@ static struct clk_regmap g12a_vpu_0 = {
static struct clk_regmap g12a_vpu_1_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_VPU_CLK_CNTL,
.mask = 0x3,
.mask = 0x7,
.shift = 25,
},
.hw.init = &(struct clk_init_data){

2
drivers/clk/meson/gxbb.c
View File

@ -2216,6 +2216,7 @@ static struct clk_regmap gxbb_vdec_1_div = {
.offset = HHI_VDEC_CLK_CNTL,
.shift = 0,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_1_div",
@ -2261,6 +2262,7 @@ static struct clk_regmap gxbb_vdec_hevc_div = {
.offset = HHI_VDEC2_CLK_CNTL,
.shift = 16,
.width = 7,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
},
.hw.init = &(struct clk_init_data){
.name = "vdec_hevc_div",