First round of fixes for meson clocks targeted for v5.1:
- g12a: Fix VPU clock parents and mux mask - gxbb: Add CLK_DIVIDER_ROUND_CLOSEST to video decoder clocks -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJckUofAAoJEHfc29rIyEnRR/AP/2a2Ps546323ryvFsJJrST1+ Lodsrds1JSc79WoibkJiRbmU82mkcfTMdcmbwGFQrEB2KQKghWfjh0XRo+SzboSy YoaGRvcc7EFkyQD6ETI1f1viBh6t94iTalfS6LclBBGx98jWVzBITrNNAzTCziJR niEtMkRvWDFMGbxxiLCbO0i3/If+37aeI0Q25nm2v9KOuYN88fgawz8hEZY74wuX 104S/+W8t9J2WUg0OCCeeXR9kHXoJ4mQGAUI9wfM/kfsQXcTVLsBgoQKC4JEKQL/ 397TkaAc7w6xr/5Z78CrN6xjFE6Dvs5SyYSDpetXf/jXSS67uHWVcSrjvixPvkFZ /y5zF6HnQYN0V6iau1CIstVYFVG6JQ3SFF2JpegJj8VnfYcycR138z2XDQLeBLVV gYYuCMUs3iwY5/gLya7lH7vmX+91mSz+vxT5+pTQfr+/WChW7PnepRmPmaTsMDaF eduoDg+hTdVDmizdnjdfHZKTBjJ6aMM4wjk+PcDv0xR8nv37bntMQaQ4kjAwoX0h o/mkhQJ0uqUoONMMzfAfkWVFVB/l4p7SP8HLg70HNKDNT3RRoJ3LcY1ZjYHPuB90 8WBas69IoVlpPRlL842x3R2Km2r/Eejk7srQt+baV80zNSIPrdky6XapZQr+HLKm ZT1ENKS88Ryrsj0l9Jwh =9jak -----END PGP SIGNATURE----- Merge tag 'meson-clk-fixes-for-5.1' of https://github.com/BayLibre/clk-meson into clk-fixes Pull a round of fixes for meson clocks from Neil Armstrong: - g12a: Fix VPU clock parents and mux mask - gxbb: Add CLK_DIVIDER_ROUND_CLOSEST to video decoder clocks * tag 'meson-clk-fixes-for-5.1' of https://github.com/BayLibre/clk-meson: clk: meson-g12a: fix VPU clock parents clk: meson: g12a: fix VPU clock muxes mask clk: meson-gxbb: round the vdec dividers to closest
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commit
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@ -960,14 +960,14 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = {
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/* VPU Clock */
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/* VPU Clock */
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static const char * const g12a_vpu_parent_names[] = {
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static const char * const g12a_vpu_parent_names[] = {
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"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
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"fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
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"mpll1", "vid_pll", "hifi_pll", "gp0_pll",
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"mpll1", "vid_pll", "hifi_pll", "gp0_pll",
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};
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};
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static struct clk_regmap g12a_vpu_0_sel = {
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static struct clk_regmap g12a_vpu_0_sel = {
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.data = &(struct clk_regmap_mux_data){
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.mask = 0x7,
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.shift = 9,
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.shift = 9,
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},
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},
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.hw.init = &(struct clk_init_data){
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.hw.init = &(struct clk_init_data){
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@ -1011,7 +1011,7 @@ static struct clk_regmap g12a_vpu_0 = {
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static struct clk_regmap g12a_vpu_1_sel = {
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static struct clk_regmap g12a_vpu_1_sel = {
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.data = &(struct clk_regmap_mux_data){
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VPU_CLK_CNTL,
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.offset = HHI_VPU_CLK_CNTL,
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.mask = 0x3,
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.mask = 0x7,
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.shift = 25,
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.shift = 25,
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},
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},
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.hw.init = &(struct clk_init_data){
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.hw.init = &(struct clk_init_data){
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@ -2216,6 +2216,7 @@ static struct clk_regmap gxbb_vdec_1_div = {
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.offset = HHI_VDEC_CLK_CNTL,
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.offset = HHI_VDEC_CLK_CNTL,
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.shift = 0,
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.shift = 0,
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.width = 7,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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},
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.hw.init = &(struct clk_init_data){
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.hw.init = &(struct clk_init_data){
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.name = "vdec_1_div",
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.name = "vdec_1_div",
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@ -2261,6 +2262,7 @@ static struct clk_regmap gxbb_vdec_hevc_div = {
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.offset = HHI_VDEC2_CLK_CNTL,
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.offset = HHI_VDEC2_CLK_CNTL,
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.shift = 16,
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.shift = 16,
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.width = 7,
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.width = 7,
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.flags = CLK_DIVIDER_ROUND_CLOSEST,
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},
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},
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.hw.init = &(struct clk_init_data){
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.hw.init = &(struct clk_init_data){
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.name = "vdec_hevc_div",
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.name = "vdec_hevc_div",
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