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highbank: Unconditionally require l2x0 L2 cache controller support 

If running in the Normal World on a TrustZone-enabled SoC, Linux
does not have complete control over the L2 cache controller
configuration.  The kernel cannot work reliably on such platforms
without the l2x0 cache support code built in.

This patch unconditionally enables l2x0 support for the Highbank
SoC.

Thanks to Rob Herring for this suggestion.  [1]

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074495.html

Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
hifive-unleashed-5.1
Dave Martin 2011-12-12 16:17:34 +00:00
parent c957445bf9
commit 22d80379e9
1 changed files with 1 additions and 1 deletions
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2
arch/arm/Kconfig
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@ -340,12 +340,12 @@ config ARCH_HIGHBANK
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
select CACHE_L2X0
select CLKDEV_LOOKUP
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select USE_OF
help
Support for the Calxeda Highbank SoC based boards.