powerpc/eeh: Sync OPAL API with firmware
The patch synchronizes OPAL APIs between kernel and firmware. Also, we starts to replace opal_pci_get_phb_diag_data() with the similar opal_pci_get_phb_diag_data2() and the former OPAL API would return OPAL_UNSUPPORTED from now on. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -117,7 +117,13 @@ extern int opal_enter_rtas(struct rtas_args *args,
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#define OPAL_SET_SLOT_LED_STATUS 55
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#define OPAL_GET_EPOW_STATUS 56
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#define OPAL_SET_SYSTEM_ATTENTION_LED 57
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#define OPAL_RESERVED1 58
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#define OPAL_RESERVED2 59
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#define OPAL_PCI_NEXT_ERROR 60
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#define OPAL_PCI_EEH_FREEZE_STATUS2 61
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#define OPAL_PCI_POLL 62
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#define OPAL_PCI_MSI_EOI 63
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#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
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#ifndef __ASSEMBLY__
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@ -125,6 +131,7 @@ extern int opal_enter_rtas(struct rtas_args *args,
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enum OpalVendorApiTokens {
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OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
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};
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enum OpalFreezeState {
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OPAL_EEH_STOPPED_NOT_FROZEN = 0,
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OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
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@ -134,55 +141,69 @@ enum OpalFreezeState {
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OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
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OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
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};
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enum OpalEehFreezeActionToken {
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OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
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OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
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OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
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};
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enum OpalPciStatusToken {
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OPAL_EEH_PHB_NO_ERROR = 0,
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OPAL_EEH_PHB_FATAL = 1,
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OPAL_EEH_PHB_RECOVERABLE = 2,
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OPAL_EEH_PHB_BUS_ERROR = 3,
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OPAL_EEH_PCI_NO_DEVSEL = 4,
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OPAL_EEH_PCI_TA = 5,
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OPAL_EEH_PCIEX_UR = 6,
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OPAL_EEH_PCIEX_CA = 7,
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OPAL_EEH_PCI_MMIO_ERROR = 8,
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OPAL_EEH_PCI_DMA_ERROR = 9
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OPAL_EEH_NO_ERROR = 0,
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OPAL_EEH_IOC_ERROR = 1,
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OPAL_EEH_PHB_ERROR = 2,
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OPAL_EEH_PE_ERROR = 3,
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OPAL_EEH_PE_MMIO_ERROR = 4,
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OPAL_EEH_PE_DMA_ERROR = 5
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};
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enum OpalPciErrorSeverity {
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OPAL_EEH_SEV_NO_ERROR = 0,
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OPAL_EEH_SEV_IOC_DEAD = 1,
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OPAL_EEH_SEV_PHB_DEAD = 2,
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OPAL_EEH_SEV_PHB_FENCED = 3,
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OPAL_EEH_SEV_PE_ER = 4,
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OPAL_EEH_SEV_INF = 5
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};
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enum OpalShpcAction {
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OPAL_SHPC_GET_LINK_STATE = 0,
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OPAL_SHPC_GET_SLOT_STATE = 1
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};
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enum OpalShpcLinkState {
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OPAL_SHPC_LINK_DOWN = 0,
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OPAL_SHPC_LINK_UP = 1
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};
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enum OpalMmioWindowType {
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OPAL_M32_WINDOW_TYPE = 1,
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OPAL_M64_WINDOW_TYPE = 2,
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OPAL_IO_WINDOW_TYPE = 3
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};
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enum OpalShpcSlotState {
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OPAL_SHPC_DEV_NOT_PRESENT = 0,
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OPAL_SHPC_DEV_PRESENT = 1
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};
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enum OpalExceptionHandler {
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OPAL_MACHINE_CHECK_HANDLER = 1,
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OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
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OPAL_SOFTPATCH_HANDLER = 3
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};
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enum OpalPendingState {
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OPAL_EVENT_OPAL_INTERNAL = 0x1,
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OPAL_EVENT_NVRAM = 0x2,
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OPAL_EVENT_RTC = 0x4,
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OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
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OPAL_EVENT_CONSOLE_INPUT = 0x10,
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OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
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OPAL_EVENT_ERROR_LOG = 0x40,
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OPAL_EVENT_EPOW = 0x80,
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OPAL_EVENT_LED_STATUS = 0x100
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OPAL_EVENT_OPAL_INTERNAL = 0x1,
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OPAL_EVENT_NVRAM = 0x2,
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OPAL_EVENT_RTC = 0x4,
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OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
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OPAL_EVENT_CONSOLE_INPUT = 0x10,
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OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
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OPAL_EVENT_ERROR_LOG = 0x40,
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OPAL_EVENT_EPOW = 0x80,
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OPAL_EVENT_LED_STATUS = 0x100,
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OPAL_EVENT_PCI_ERROR = 0x200
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};
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/* Machine check related definitions */
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@ -364,15 +385,80 @@ struct opal_machine_check_event {
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} u;
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};
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enum {
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OPAL_P7IOC_DIAG_TYPE_NONE = 0,
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OPAL_P7IOC_DIAG_TYPE_RGC = 1,
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OPAL_P7IOC_DIAG_TYPE_BI = 2,
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OPAL_P7IOC_DIAG_TYPE_CI = 3,
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OPAL_P7IOC_DIAG_TYPE_MISC = 4,
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OPAL_P7IOC_DIAG_TYPE_I2C = 5,
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OPAL_P7IOC_DIAG_TYPE_LAST = 6
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};
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struct OpalIoP7IOCErrorData {
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uint16_t type;
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/* GEM */
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uint64_t gemXfir;
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uint64_t gemRfir;
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uint64_t gemRirqfir;
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uint64_t gemMask;
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uint64_t gemRwof;
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/* LEM */
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uint64_t lemFir;
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uint64_t lemErrMask;
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uint64_t lemAction0;
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uint64_t lemAction1;
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uint64_t lemWof;
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union {
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struct OpalIoP7IOCRgcErrorData {
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uint64_t rgcStatus; /* 3E1C10 */
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uint64_t rgcLdcp; /* 3E1C18 */
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}rgc;
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struct OpalIoP7IOCBiErrorData {
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uint64_t biLdcp0; /* 3C0100, 3C0118 */
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uint64_t biLdcp1; /* 3C0108, 3C0120 */
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uint64_t biLdcp2; /* 3C0110, 3C0128 */
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uint64_t biFenceStatus; /* 3C0130, 3C0130 */
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uint8_t biDownbound; /* BI Downbound or Upbound */
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}bi;
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struct OpalIoP7IOCCiErrorData {
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uint64_t ciPortStatus; /* 3Dn008 */
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uint64_t ciPortLdcp; /* 3Dn010 */
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uint8_t ciPort; /* Index of CI port: 0/1 */
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}ci;
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};
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};
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/**
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* This structure defines the overlay which will be used to store PHB error
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* data upon request.
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*/
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enum {
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OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
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};
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enum {
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OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
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};
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enum {
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OPAL_P7IOC_NUM_PEST_REGS = 128,
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};
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struct OpalIoPhbErrorCommon {
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uint32_t version;
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uint32_t ioType;
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uint32_t len;
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};
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struct OpalIoP7IOCPhbErrorData {
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struct OpalIoPhbErrorCommon common;
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uint32_t brdgCtl;
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// P7IOC utl regs
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@ -530,14 +616,21 @@ int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
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uint64_t pci_mem_size);
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int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
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int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
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int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
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int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
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uint64_t diag_buffer_len);
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int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
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uint64_t diag_buffer_len);
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int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
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uint64_t diag_buffer_len);
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int64_t opal_pci_fence_phb(uint64_t phb_id);
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int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
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int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
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int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
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int64_t opal_get_epow_status(uint64_t *status);
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int64_t opal_set_system_attention_led(uint8_t led_action);
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int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
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uint16_t *pci_error_type, uint16_t *severity);
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int64_t opal_pci_poll(uint64_t phb_id);
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/* Internal functions */
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extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
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@ -107,4 +107,7 @@ OPAL_CALL(opal_pci_mask_pe_error, OPAL_PCI_MASK_PE_ERROR);
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OPAL_CALL(opal_set_slot_led_status, OPAL_SET_SLOT_LED_STATUS);
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OPAL_CALL(opal_get_epow_status, OPAL_GET_EPOW_STATUS);
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OPAL_CALL(opal_set_system_attention_led, OPAL_SET_SYSTEM_ATTENTION_LED);
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OPAL_CALL(opal_pci_next_error, OPAL_PCI_NEXT_ERROR);
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OPAL_CALL(opal_pci_poll, OPAL_PCI_POLL);
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OPAL_CALL(opal_pci_msi_eoi, OPAL_PCI_MSI_EOI);
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OPAL_CALL(opal_pci_get_phb_diag_data2, OPAL_PCI_GET_PHB_DIAG_DATA2);
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@ -203,7 +203,8 @@ static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
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spin_lock_irqsave(&phb->lock, flags);
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rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
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rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
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PNV_PCI_DIAG_BUF_SIZE);
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has_diag = (rc == OPAL_SUCCESS);
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rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
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