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Merge branch 'core/urgent' into x86/urgent, to pick up objtool fix 

Signed-off-by: Ingo Molnar <mingo@kernel.org>
hifive-unleashed-5.1
Ingo Molnar 2018-11-03 23:42:16 +01:00
parent 98f76206b3 bcb6fb5da7
commit 23a12ddee1
4068 changed files with 262354 additions and 74077 deletions
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1
.clang-format
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@ -323,7 +323,6 @@ ForEachMacros:
- 'protocol_for_each_card'
- 'protocol_for_each_dev'
- 'queue_for_each_hw_ctx'
- 'radix_tree_for_each_contig'
- 'radix_tree_for_each_slot'
- 'radix_tree_for_each_tagged'
- 'rbtree_postorder_for_each_entry_safe'

12
.mailmap
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@ -119,6 +119,13 @@ Mark Brown <broonie@sirena.org.uk>
Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>
Matthew Wilcox <willy@infradead.org> <mawilcox@linuxonhyperv.com>
Matthew Wilcox <willy@infradead.org> <mawilcox@microsoft.com>
Matthew Wilcox <willy@infradead.org> <willy@debian.org>
Matthew Wilcox <willy@infradead.org> <willy@linux.intel.com>
Matthew Wilcox <willy@infradead.org> <willy@parisc-linux.org>
Matthieu CASTET <castet.matthieu@free.fr>
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>
Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>
@ -153,6 +160,11 @@ Peter Oruba <peter.oruba@amd.com>
Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
Praveen BP <praveenbp@ti.com>
Qais Yousef <qsyousef@gmail.com> <qais.yousef@imgtec.com>
Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net>
Oleksij Rempel <linux@rempel-privat.de> <external.Oleksij.Rempel@de.bosch.com>
Oleksij Rempel <linux@rempel-privat.de> <fixed-term.Oleksij.Rempel@de.bosch.com>
Oleksij Rempel <linux@rempel-privat.de> <o.rempel@pengutronix.de>
Oleksij Rempel <linux@rempel-privat.de> <ore@pengutronix.de>
Rajesh Shah <rajesh.shah@intel.com>
Ralf Baechle <ralf@linux-mips.org>
Ralf Wildenhues <Ralf.Wildenhues@gmx.de>

2
Documentation/ABI/testing/sysfs-bus-iio
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@ -199,7 +199,7 @@ Description:
What: /sys/bus/iio/devices/iio:deviceX/in_positionrelative_x_raw
What: /sys/bus/iio/devices/iio:deviceX/in_positionrelative_y_raw
KernelVersion: 4.18
KernelVersion: 4.19
Contact: linux-iio@vger.kernel.org
Description:
Relative position in direction x or y on a pad (may be

42
Documentation/admin-guide/mm/memory-hotplug.rst
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@ -5,7 +5,7 @@ Memory Hotplug
==============
:Created: Jul 28 2007
:Updated: Add description of notifier of memory hotplug: Oct 11 2007
:Updated: Add some details about locking internals: Aug 20 2018
This document is about memory hotplug including how-to-use and current status.
Because Memory Hotplug is still under development, contents of this text will
@ -392,6 +392,46 @@ Need more implementation yet....
- Notification completion of remove works by OS to firmware.
- Guard from remove if not yet.
Locking Internals
=================
When adding/removing memory that uses memory block devices (i.e. ordinary RAM),
the device_hotplug_lock should be held to:
- synchronize against online/offline requests (e.g. via sysfs). This way, memory
block devices can only be accessed (.online/.state attributes) by user
space once memory has been fully added. And when removing memory, we
know nobody is in critical sections.
- synchronize against CPU hotplug and similar (e.g. relevant for ACPI and PPC)
Especially, there is a possible lock inversion that is avoided using
device_hotplug_lock when adding memory and user space tries to online that
memory faster than expected:
- device_online() will first take the device_lock(), followed by
mem_hotplug_lock
- add_memory_resource() will first take the mem_hotplug_lock, followed by
the device_lock() (while creating the devices, during bus_add_device()).
As the device is visible to user space before taking the device_lock(), this
can result in a lock inversion.
onlining/offlining of memory should be done via device_online()/
device_offline() - to make sure it is properly synchronized to actions
via sysfs. Holding device_hotplug_lock is advised (to e.g. protect online_type)
When adding/removing/onlining/offlining memory or adding/removing
heterogeneous/device memory, we should always hold the mem_hotplug_lock in
write mode to serialise memory hotplug (e.g. access to global/zone
variables).
In addition, mem_hotplug_lock (in contrast to device_hotplug_lock) in read
mode allows for a quite efficient get_online_mems/put_online_mems
implementation, so code accessing memory can protect from that memory
vanishing.
Future Work
===========

1
Documentation/arm/Samsung/Bootloader-interface.txt
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@ -26,6 +26,7 @@ Offset Value Purpose
0x20 0xfcba0d10 (Magic cookie) AFTR
0x24 exynos_cpu_resume_ns AFTR
0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
0x28 0x0 or last value during resume (Exynos542x) System suspend
2. Secure mode

69
Documentation/core-api/boot-time-mm.rst
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@ -5,54 +5,23 @@ Boot time memory management
Early system initialization cannot use "normal" memory management
simply because it is not set up yet. But there is still need to
allocate memory for various data structures, for instance for the
physical page allocator. To address this, a specialized allocator
called the :ref:`Boot Memory Allocator <bootmem>`, or bootmem, was
introduced. Several years later PowerPC developers added a "Logical
Memory Blocks" allocator, which was later adopted by other
architectures and renamed to :ref:`memblock <memblock>`. There is also
a compatibility layer called `nobootmem` that translates bootmem
allocation interfaces to memblock calls.
physical page allocator.
The selection of the early allocator is done using
``CONFIG_NO_BOOTMEM`` and ``CONFIG_HAVE_MEMBLOCK`` kernel
configuration options. These options are enabled or disabled
statically by the architectures' Kconfig files.
* Architectures that rely only on bootmem select
``CONFIG_NO_BOOTMEM=n && CONFIG_HAVE_MEMBLOCK=n``.
* The users of memblock with the nobootmem compatibility layer set
``CONFIG_NO_BOOTMEM=y && CONFIG_HAVE_MEMBLOCK=y``.
* And for those that use both memblock and bootmem the configuration
includes ``CONFIG_NO_BOOTMEM=n && CONFIG_HAVE_MEMBLOCK=y``.
Whichever allocator is used, it is the responsibility of the
architecture specific initialization to set it up in
:c:func:`setup_arch` and tear it down in :c:func:`mem_init` functions.
A specialized allocator called ``memblock`` performs the
boot time memory management. The architecture specific initialization
must set it up in :c:func:`setup_arch` and tear it down in
:c:func:`mem_init` functions.
Once the early memory management is available it offers a variety of
functions and macros for memory allocations. The allocation request
may be directed to the first (and probably the only) node or to a
particular node in a NUMA system. There are API variants that panic
when an allocation fails and those that don't. And more recent and
advanced memblock even allows controlling its own behaviour.
when an allocation fails and those that don't.
.. _bootmem:
Memblock also offers a variety of APIs that control its own behaviour.
Bootmem
=======
(mostly stolen from Mel Gorman's "Understanding the Linux Virtual
Memory Manager" `book`_)
.. _book: https://www.kernel.org/doc/gorman/
.. kernel-doc:: mm/bootmem.c
:doc: bootmem overview
.. _memblock:
Memblock
========
Memblock Overview
=================
.. kernel-doc:: mm/memblock.c
:doc: memblock overview
@ -61,26 +30,6 @@ Memblock
Functions and structures
========================
Common API
----------
The functions that are described in this section are available
regardless of what early memory manager is enabled.
.. kernel-doc:: mm/nobootmem.c
Bootmem specific API
--------------------
These interfaces available only with bootmem, i.e when ``CONFIG_NO_BOOTMEM=n``
.. kernel-doc:: include/linux/bootmem.h
.. kernel-doc:: mm/bootmem.c
:functions:
Memblock specific API
---------------------
Here is the description of memblock data structures, functions and
macros. Some of them are actually internal, but since they are
documented it would be silly to omit them. Besides, reading the

1
Documentation/core-api/index.rst
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@ -21,6 +21,7 @@ Core utilities
local_ops
workqueue
genericirq
xarray
flexible-arrays
librs
genalloc

435
Documentation/core-api/xarray.rst 100644
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@ -0,0 +1,435 @@
.. SPDX-License-Identifier: GPL-2.0+
======
XArray
======
:Author: Matthew Wilcox
Overview
========
The XArray is an abstract data type which behaves like a very large array
of pointers. It meets many of the same needs as a hash or a conventional
resizable array. Unlike a hash, it allows you to sensibly go to the
next or previous entry in a cache-efficient manner. In contrast to a
resizable array, there is no need to copy data or change MMU mappings in
order to grow the array. It is more memory-efficient, parallelisable
and cache friendly than a doubly-linked list. It takes advantage of
RCU to perform lookups without locking.
The XArray implementation is efficient when the indices used are densely
clustered; hashing the object and using the hash as the index will not
perform well. The XArray is optimised for small indices, but still has
good performance with large indices. If your index can be larger than
``ULONG_MAX`` then the XArray is not the data type for you. The most
important user of the XArray is the page cache.
Each non-``NULL`` entry in the array has three bits associated with
it called marks. Each mark may be set or cleared independently of
the others. You can iterate over entries which are marked.
Normal pointers may be stored in the XArray directly. They must be 4-byte
aligned, which is true for any pointer returned from :c:func:`kmalloc` and
:c:func:`alloc_page`. It isn't true for arbitrary user-space pointers,
nor for function pointers. You can store pointers to statically allocated
objects, as long as those objects have an alignment of at least 4.
You can also store integers between 0 and ``LONG_MAX`` in the XArray.
You must first convert it into an entry using :c:func:`xa_mk_value`.
When you retrieve an entry from the XArray, you can check whether it is
a value entry by calling :c:func:`xa_is_value`, and convert it back to
an integer by calling :c:func:`xa_to_value`.
Some users want to store tagged pointers instead of using the marks
described above. They can call :c:func:`xa_tag_pointer` to create an
entry with a tag, :c:func:`xa_untag_pointer` to turn a tagged entry
back into an untagged pointer and :c:func:`xa_pointer_tag` to retrieve
the tag of an entry. Tagged pointers use the same bits that are used
to distinguish value entries from normal pointers, so each user must
decide whether they want to store value entries or tagged pointers in
any particular XArray.
The XArray does not support storing :c:func:`IS_ERR` pointers as some
conflict with value entries or internal entries.
An unusual feature of the XArray is the ability to create entries which
occupy a range of indices. Once stored to, looking up any index in
the range will return the same entry as looking up any other index in
the range. Setting a mark on one index will set it on all of them.
Storing to any index will store to all of them. Multi-index entries can
be explicitly split into smaller entries, or storing ``NULL`` into any
entry will cause the XArray to forget about the range.
Normal API
==========
Start by initialising an XArray, either with :c:func:`DEFINE_XARRAY`
for statically allocated XArrays or :c:func:`xa_init` for dynamically
allocated ones. A freshly-initialised XArray contains a ``NULL``
pointer at every index.
You can then set entries using :c:func:`xa_store` and get entries
using :c:func:`xa_load`. xa_store will overwrite any entry with the
new entry and return the previous entry stored at that index. You can
use :c:func:`xa_erase` instead of calling :c:func:`xa_store` with a
``NULL`` entry. There is no difference between an entry that has never
been stored to and one that has most recently had ``NULL`` stored to it.
You can conditionally replace an entry at an index by using
:c:func:`xa_cmpxchg`. Like :c:func:`cmpxchg`, it will only succeed if
the entry at that index has the 'old' value. It also returns the entry
which was at that index; if it returns the same entry which was passed as
'old', then :c:func:`xa_cmpxchg` succeeded.
If you want to only store a new entry to an index if the current entry
at that index is ``NULL``, you can use :c:func:`xa_insert` which
returns ``-EEXIST`` if the entry is not empty.
You can enquire whether a mark is set on an entry by using
:c:func:`xa_get_mark`. If the entry is not ``NULL``, you can set a mark
on it by using :c:func:`xa_set_mark` and remove the mark from an entry by
calling :c:func:`xa_clear_mark`. You can ask whether any entry in the
XArray has a particular mark set by calling :c:func:`xa_marked`.
You can copy entries out of the XArray into a plain array by calling
:c:func:`xa_extract`. Or you can iterate over the present entries in
the XArray by calling :c:func:`xa_for_each`. You may prefer to use
:c:func:`xa_find` or :c:func:`xa_find_after` to move to the next present
entry in the XArray.
Calling :c:func:`xa_store_range` stores the same entry in a range
of indices. If you do this, some of the other operations will behave
in a slightly odd way. For example, marking the entry at one index
may result in the entry being marked at some, but not all of the other
indices. Storing into one index may result in the entry retrieved by
some, but not all of the other indices changing.
Finally, you can remove all entries from an XArray by calling
:c:func:`xa_destroy`. If the XArray entries are pointers, you may wish
to free the entries first. You can do this by iterating over all present
entries in the XArray using the :c:func:`xa_for_each` iterator.
ID assignment
-------------
You can call :c:func:`xa_alloc` to store the entry at any unused index
in the XArray. If you need to modify the array from interrupt context,
you can use :c:func:`xa_alloc_bh` or :c:func:`xa_alloc_irq` to disable
interrupts while allocating the ID. Unlike :c:func:`xa_store`, allocating
a ``NULL`` pointer does not delete an entry. Instead it reserves an
entry like :c:func:`xa_reserve` and you can release it using either
:c:func:`xa_erase` or :c:func:`xa_release`. To use ID assignment, the
XArray must be defined with :c:func:`DEFINE_XARRAY_ALLOC`, or initialised
by passing ``XA_FLAGS_ALLOC`` to :c:func:`xa_init_flags`,
Memory allocation
-----------------
The :c:func:`xa_store`, :c:func:`xa_cmpxchg`, :c:func:`xa_alloc`,
:c:func:`xa_reserve` and :c:func:`xa_insert` functions take a gfp_t
parameter in case the XArray needs to allocate memory to store this entry.
If the entry is being deleted, no memory allocation needs to be performed,
and the GFP flags specified will be ignored.
It is possible for no memory to be allocatable, particularly if you pass
a restrictive set of GFP flags. In that case, the functions return a
special value which can be turned into an errno using :c:func:`xa_err`.
If you don't need to know exactly which error occurred, using
:c:func:`xa_is_err` is slightly more efficient.
Locking
-------
When using the Normal API, you do not have to worry about locking.
The XArray uses RCU and an internal spinlock to synchronise access:
No lock needed:
* :c:func:`xa_empty`
* :c:func:`xa_marked`
Takes RCU read lock:
* :c:func:`xa_load`
* :c:func:`xa_for_each`
* :c:func:`xa_find`
* :c:func:`xa_find_after`
* :c:func:`xa_extract`
* :c:func:`xa_get_mark`
Takes xa_lock internally:
* :c:func:`xa_store`
* :c:func:`xa_insert`
* :c:func:`xa_erase`
* :c:func:`xa_erase_bh`
* :c:func:`xa_erase_irq`
* :c:func:`xa_cmpxchg`
* :c:func:`xa_store_range`
* :c:func:`xa_alloc`
* :c:func:`xa_alloc_bh`
* :c:func:`xa_alloc_irq`
* :c:func:`xa_destroy`
* :c:func:`xa_set_mark`
* :c:func:`xa_clear_mark`
Assumes xa_lock held on entry:
* :c:func:`__xa_store`
* :c:func:`__xa_insert`
* :c:func:`__xa_erase`
* :c:func:`__xa_cmpxchg`
* :c:func:`__xa_alloc`
* :c:func:`__xa_set_mark`
* :c:func:`__xa_clear_mark`
If you want to take advantage of the lock to protect the data structures
that you are storing in the XArray, you can call :c:func:`xa_lock`
before calling :c:func:`xa_load`, then take a reference count on the
object you have found before calling :c:func:`xa_unlock`. This will
prevent stores from removing the object from the array between looking
up the object and incrementing the refcount. You can also use RCU to
avoid dereferencing freed memory, but an explanation of that is beyond
the scope of this document.
The XArray does not disable interrupts or softirqs while modifying
the array. It is safe to read the XArray from interrupt or softirq
context as the RCU lock provides enough protection.
If, for example, you want to store entries in the XArray in process
context and then erase them in softirq context, you can do that this way::
void foo_init(struct foo *foo)
{
xa_init_flags(&foo->array, XA_FLAGS_LOCK_BH);
}
int foo_store(struct foo *foo, unsigned long index, void *entry)
{
int err;
xa_lock_bh(&foo->array);
err = xa_err(__xa_store(&foo->array, index, entry, GFP_KERNEL));
if (!err)
foo->count++;
xa_unlock_bh(&foo->array);
return err;
}
/* foo_erase() is only called from softirq context */
void foo_erase(struct foo *foo, unsigned long index)
{
xa_lock(&foo->array);
__xa_erase(&foo->array, index);
foo->count--;
xa_unlock(&foo->array);
}
If you are going to modify the XArray from interrupt or softirq context,
you need to initialise the array using :c:func:`xa_init_flags`, passing
``XA_FLAGS_LOCK_IRQ`` or ``XA_FLAGS_LOCK_BH``.
The above example also shows a common pattern of wanting to extend the
coverage of the xa_lock on the store side to protect some statistics
associated with the array.
Sharing the XArray with interrupt context is also possible, either
using :c:func:`xa_lock_irqsave` in both the interrupt handler and process
context, or :c:func:`xa_lock_irq` in process context and :c:func:`xa_lock`
in the interrupt handler. Some of the more common patterns have helper
functions such as :c:func:`xa_erase_bh` and :c:func:`xa_erase_irq`.
Sometimes you need to protect access to the XArray with a mutex because
that lock sits above another mutex in the locking hierarchy. That does
not entitle you to use functions like :c:func:`__xa_erase` without taking
the xa_lock; the xa_lock is used for lockdep validation and will be used
for other purposes in the future.
The :c:func:`__xa_set_mark` and :c:func:`__xa_clear_mark` functions are also
available for situations where you look up an entry and want to atomically
set or clear a mark. It may be more efficient to use the advanced API
in this case, as it will save you from walking the tree twice.
Advanced API
============
The advanced API offers more flexibility and better performance at the
cost of an interface which can be harder to use and has fewer safeguards.
No locking is done for you by the advanced API, and you are required
to use the xa_lock while modifying the array. You can choose whether
to use the xa_lock or the RCU lock while doing read-only operations on
the array. You can mix advanced and normal operations on the same array;
indeed the normal API is implemented in terms of the advanced API. The
advanced API is only available to modules with a GPL-compatible license.
The advanced API is based around the xa_state. This is an opaque data
structure which you declare on the stack using the :c:func:`XA_STATE`
macro. This macro initialises the xa_state ready to start walking
around the XArray. It is used as a cursor to maintain the position
in the XArray and let you compose various operations together without
having to restart from the top every time.
The xa_state is also used to store errors. You can call
:c:func:`xas_error` to retrieve the error. All operations check whether
the xa_state is in an error state before proceeding, so there's no need
for you to check for an error after each call; you can make multiple
calls in succession and only check at a convenient point. The only
errors currently generated by the XArray code itself are ``ENOMEM`` and
``EINVAL``, but it supports arbitrary errors in case you want to call
:c:func:`xas_set_err` yourself.
If the xa_state is holding an ``ENOMEM`` error, calling :c:func:`xas_nomem`
will attempt to allocate more memory using the specified gfp flags and
cache it in the xa_state for the next attempt. The idea is that you take
the xa_lock, attempt the operation and drop the lock. The operation
attempts to allocate memory while holding the lock, but it is more
likely to fail. Once you have dropped the lock, :c:func:`xas_nomem`
can try harder to allocate more memory. It will return ``true`` if it
is worth retrying the operation (i.e. that there was a memory error *and*
more memory was allocated). If it has previously allocated memory, and
that memory wasn't used, and there is no error (or some error that isn't
``ENOMEM``), then it will free the memory previously allocated.
Internal Entries
----------------
The XArray reserves some entries for its own purposes. These are never
exposed through the normal API, but when using the advanced API, it's
possible to see them. Usually the best way to handle them is to pass them
to :c:func:`xas_retry`, and retry the operation if it returns ``true``.
.. flat-table::
:widths: 1 1 6
* - Name
- Test
- Usage
* - Node
- :c:func:`xa_is_node`
- An XArray node. May be visible when using a multi-index xa_state.
* - Sibling
- :c:func:`xa_is_sibling`
- A non-canonical entry for a multi-index entry. The value indicates
which slot in this node has the canonical entry.
* - Retry
- :c:func:`xa_is_retry`
- This entry is currently being modified by a thread which has the
xa_lock. The node containing this entry may be freed at the end
of this RCU period. You should restart the lookup from the head
of the array.
* - Zero
- :c:func:`xa_is_zero`
- Zero entries appear as ``NULL`` through the Normal API, but occupy
an entry in the XArray which can be used to reserve the index for
future use.
Other internal entries may be added in the future. As far as possible, they
will be handled by :c:func:`xas_retry`.
Additional functionality
------------------------
The :c:func:`xas_create_range` function allocates all the necessary memory
to store every entry in a range. It will set ENOMEM in the xa_state if
it cannot allocate memory.
You can use :c:func:`xas_init_marks` to reset the marks on an entry
to their default state. This is usually all marks clear, unless the
XArray is marked with ``XA_FLAGS_TRACK_FREE``, in which case mark 0 is set
and all other marks are clear. Replacing one entry with another using
:c:func:`xas_store` will not reset the marks on that entry; if you want
the marks reset, you should do that explicitly.
The :c:func:`xas_load` will walk the xa_state as close to the entry
as it can. If you know the xa_state has already been walked to the
entry and need to check that the entry hasn't changed, you can use
:c:func:`xas_reload` to save a function call.
If you need to move to a different index in the XArray, call
:c:func:`xas_set`. This resets the cursor to the top of the tree, which
will generally make the next operation walk the cursor to the desired
spot in the tree. If you want to move to the next or previous index,
call :c:func:`xas_next` or :c:func:`xas_prev`. Setting the index does
not walk the cursor around the array so does not require a lock to be
held, while moving to the next or previous index does.
You can search for the next present entry using :c:func:`xas_find`. This
is the equivalent of both :c:func:`xa_find` and :c:func:`xa_find_after`;
if the cursor has been walked to an entry, then it will find the next
entry after the one currently referenced. If not, it will return the
entry at the index of the xa_state. Using :c:func:`xas_next_entry` to
move to the next present entry instead of :c:func:`xas_find` will save
a function call in the majority of cases at the expense of emitting more
inline code.
The :c:func:`xas_find_marked` function is similar. If the xa_state has
not been walked, it will return the entry at the index of the xa_state,
if it is marked. Otherwise, it will return the first marked entry after
the entry referenced by the xa_state. The :c:func:`xas_next_marked`
function is the equivalent of :c:func:`xas_next_entry`.
When iterating over a range of the XArray using :c:func:`xas_for_each`
or :c:func:`xas_for_each_marked`, it may be necessary to temporarily stop
the iteration. The :c:func:`xas_pause` function exists for this purpose.
After you have done the necessary work and wish to resume, the xa_state
is in an appropriate state to continue the iteration after the entry
you last processed. If you have interrupts disabled while iterating,
then it is good manners to pause the iteration and reenable interrupts
every ``XA_CHECK_SCHED`` entries.
The :c:func:`xas_get_mark`, :c:func:`xas_set_mark` and
:c:func:`xas_clear_mark` functions require the xa_state cursor to have
been moved to the appropriate location in the xarray; they will do
nothing if you have called :c:func:`xas_pause` or :c:func:`xas_set`
immediately before.
You can call :c:func:`xas_set_update` to have a callback function
called each time the XArray updates a node. This is used by the page
cache workingset code to maintain its list of nodes which contain only
shadow entries.
Multi-Index Entries
-------------------
The XArray has the ability to tie multiple indices together so that
operations on one index affect all indices. For example, storing into
any index will change the value of the entry retrieved from any index.
Setting or clearing a mark on any index will set or clear the mark
on every index that is tied together. The current implementation
only allows tying ranges which are aligned powers of two together;
eg indices 64-127 may be tied together, but 2-6 may not be. This may
save substantial quantities of memory; for example tying 512 entries
together will save over 4kB.
You can create a multi-index entry by using :c:func:`XA_STATE_ORDER`
or :c:func:`xas_set_order` followed by a call to :c:func:`xas_store`.
Calling :c:func:`xas_load` with a multi-index xa_state will walk the
xa_state to the right location in the tree, but the return value is not
meaningful, potentially being an internal entry or ``NULL`` even when there
is an entry stored within the range. Calling :c:func:`xas_find_conflict`
will return the first entry within the range or ``NULL`` if there are no
entries in the range. The :c:func:`xas_for_each_conflict` iterator will
iterate over every entry which overlaps the specified range.
If :c:func:`xas_load` encounters a multi-index entry, the xa_index
in the xa_state will not be changed. When iterating over an XArray
or calling :c:func:`xas_find`, if the initial index is in the middle
of a multi-index entry, it will not be altered. Subsequent calls
or iterations will move the index to the first index in the range.
Each entry will only be returned once, no matter how many indices it
occupies.
Using :c:func:`xas_next` or :c:func:`xas_prev` with a multi-index xa_state
is not supported. Using either of these functions on a multi-index entry
will reveal sibling entries; these should be skipped over by the caller.
Storing ``NULL`` into any index of a multi-index entry will set the entry
at every index to ``NULL`` and dissolve the tie. Splitting a multi-index
entry into entries occupying smaller ranges is not yet supported.
Functions and structures
========================
.. kernel-doc:: include/linux/xarray.h
.. kernel-doc:: lib/xarray.c

7
Documentation/devicetree/bindings/arm/amlogic.txt
View File

@ -57,12 +57,17 @@ Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,a113d", "amlogic,meson-axg";
Boards with the Amlogic Meson G12A S905D2 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,g12a";
Board compatible values (alphabetically, grouped by SoC):
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
- "endless,ec100" (Meson8b)
- "hardkernel,odroid-c1" (Meson8b)
- "tronfy,mxq" (Meson8b)
@ -101,6 +106,8 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,s400" (Meson axg a113d)
- "amlogic,u200" (Meson g12a s905d2)
Amlogic Meson Firmware registers Interface
------------------------------------------

8
Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
View File

@ -42,6 +42,14 @@ Raspberry Pi Compute Module
Required root node properties:
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
Raspberry Pi Compute Module 3
Required root node properties:
compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
Raspberry Pi Compute Module 3 Lite
Required root node properties:
compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";
Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";

183
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt 100644
View File

@ -0,0 +1,183 @@
NXP i.MX System Controller Firmware (SCFW)
--------------------------------------------------------------------
The System Controller Firmware (SCFW) is a low-level system function
which runs on a dedicated Cortex-M core to provide power, clock, and
resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
(QM, QP), and i.MX8QX (QXP, DX).
The AP communicates with the SC using a multi-ported MU module found
in the LSIO subsystem. The current definition of this MU module provides
5 remote AP connections to the SC to support up to 5 execution environments
(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
with the LSIO DSC IP bus. The SC firmware will communicate with this MU
using the MSI bus.
System Controller Device Node:
============================================================
The scu node with the following properties shall be under the /firmware/ node.
Required properties:
-------------------
- compatible: should be "fsl,imx-scu".
- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
"rx0", "rx1", "rx2", "rx3".
- mboxes: List of phandle of 4 MU channels for tx and 4 MU channels
for rx. All 8 MU channels must be in the same MU instance.
Cross instances are not allowed. The MU instance can only
be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
to make sure use the one which is not conflict with other
execution environments. e.g. ATF.
Note:
Channel 0 must be "tx0" or "rx0".
Channel 1 must be "tx1" or "rx1".
Channel 2 must be "tx2" or "rx2".
Channel 3 must be "tx3" or "rx3".
e.g.
mboxes = <&lsio_mu1 0 0
&lsio_mu1 0 1
&lsio_mu1 0 2
&lsio_mu1 0 3
&lsio_mu1 1 0
&lsio_mu1 1 1
&lsio_mu1 1 2
&lsio_mu1 1 3>;
See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
for detailed mailbox binding.
i.MX SCU Client Device Node:
============================================================
Client nodes are maintained as children of the relevant IMX-SCU device node.
Power domain bindings based on SCU Message Protocol
------------------------------------------------------------
This binding for the SCU power domain providers uses the generic power
domain binding[2].
Required properties:
- compatible: Should be "fsl,scu-pd".
- #address-cells: Should be 1.
- #size-cells: Should be 0.
Required properties for power domain sub nodes:
- #power-domain-cells: Must be 0.
Optional Properties:
- reg: Resource ID of this power domain.
No exist means uncontrollable by user.
See detailed Resource ID list from:
include/dt-bindings/power/imx-rsrc.h
- power-domains: phandle pointing to the parent power domain.
Clock bindings based on SCU Message Protocol
------------------------------------------------------------
This binding uses the common clock binding[1].
Required properties:
- compatible: Should be "fsl,imx8qxp-clock".
- #clock-cells: Should be 1. Contains the Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell.
See the full list of clock IDs from:
include/dt-bindings/clock/imx8qxp-clock.h
Pinctrl bindings based on SCU Message Protocol
------------------------------------------------------------
This binding uses the i.MX common pinctrl binding[3].
Required properties:
- compatible: Should be "fsl,imx8qxp-iomuxc".
Required properties for Pinctrl sub nodes:
- fsl,pins: Each entry consists of 3 integers which represents
the mux and config setting for one pin. The first 2
integers <pin_id mux_mode> are specified using a
PIN_FUNC_ID macro, which can be found in
<dt-bindings/pinctrl/pads-imx8qxp.h>.
The last integer CONFIG is the pad setting value like
pull-up on this pin.
Please refer to i.MX8QXP Reference Manual for detailed
CONFIG settings.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/power/power_domain.txt
[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
Example (imx8qxp):
-------------
lsio_mu1: mailbox@5d1c0000 {
...
#mbox-cells = <2>;
};
firmware {
scu {
compatible = "fsl,imx-scu";
mbox-names = "tx0", "tx1", "tx2", "tx3",
"rx0", "rx1", "rx2", "rx3";
mboxes = <&lsio_mu1 0 0
&lsio_mu1 0 1
&lsio_mu1 0 2
&lsio_mu1 0 3
&lsio_mu1 1 0
&lsio_mu1 1 1
&lsio_mu1 1 2
&lsio_mu1 1 3>;
clk: clk {
compatible = "fsl,imx8qxp-clk";
#clock-cells = <1>;
};
iomuxc {
compatible = "fsl,imx8qxp-iomuxc";
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
...
};
imx8qx-pm {
compatible = "fsl,scu-pd";
#address-cells = <1>;
#size-cells = <0>;
pd_dma: dma-power-domain {
#power-domain-cells = <0>;
pd_dma_lpuart0: dma-lpuart0@57 {
reg = <SC_R_UART_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
...
};
...
};
};
};
serial@5a060000 {
...
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
clocks = <&clk IMX8QXP_UART0_CLK>,
<&clk IMX8QXP_UART0_IPG_CLK>;
clock-names = "per", "ipg";
power-domains = <&pd_dma_lpuart0>;
};

44
Documentation/devicetree/bindings/arm/fsl.txt
View File

@ -57,6 +57,50 @@ i.MX6SLL EVK board
Required root node properties:
- compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
i.MX6 Quad Plus SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
i.MX6 Quad Plus SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
i.MX6 DualLite SABRE Smart Device Board
Required root node properties:
- compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
i.MX6 DualLite/Solo SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
i.MX6 SoloLite EVK Board
Required root node properties:
- compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
i.MX6 UltraLite 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
i.MX6 UltraLiteLite 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
i.MX6 ULZ 14x14 EVK Board
Required root node properties:
- compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
i.MX6 SoloX SDB Board
Required root node properties:
- compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
i.MX6 SoloX Sabre Auto Board
Required root node properties:
- compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
i.MX7 SabreSD Board
Required root node properties:
- compatible = "fsl,imx7d-sdb", "fsl,imx7d";
Generic i.MX boards
-------------------

8
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View File

@ -8,6 +8,14 @@ HiKey960 Board
Required root node properties:
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
Hi3670 SoC
Required root node properties:
- compatible = "hisilicon,hi3670";
HiKey970 Board
Required root node properties:
- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";

4
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
View File

@ -45,11 +45,15 @@ Optional Properties:
debug_messages - Map the Debug message region
- reg: register space corresponding to the debug_messages
- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
- ti,host-id: Integer value corresponding to the host ID assigned by Firmware
for identification of host processing entities such as virtual
machines
Example (K2G):
-------------
pmmc: pmmc {
compatible = "ti,k2g-sci";
ti,host-id = <2>;
mbox-names = "rx", "tx";
mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
<&msgmgr &msgmgr_proxy_pmmc_tx>;

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2712-apmixedsys", "syscon"
- "mediatek,mt6797-apmixedsys"
- "mediatek,mt7622-apmixedsys"
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
View File

@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
- #clock-cells: Must be 1
The AUDSYS controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
View File

@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-bdpsys", "syscon"
- "mediatek,mt2712-bdpsys", "syscon"
- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1
The bdpsys controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
View File

@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-hifsys", "syscon"
- "mediatek,mt7622-hifsys", "syscon"
- "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1
The hifsys controller uses the common clk binding from

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt2712-imgsys", "syscon"
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
View File

@ -11,6 +11,7 @@ Required Properties:
- "mediatek,mt2712-infracfg", "syscon"
- "mediatek,mt6797-infracfg", "syscon"
- "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt2712-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt2712-pericfg", "syscon"
- "mediatek,mt7622-pericfg", "syscon"
- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
View File

@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt2712-topckgen", "syscon"
- "mediatek,mt6797-topckgen"
- "mediatek,mt7622-topckgen"
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
- #clock-cells: Must be 1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
View File

@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt2712-vdecsys", "syscon"
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- #clock-cells: Must be 1

19
Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
View File

@ -21,10 +21,29 @@ PROPERTIES
the register region. An optional second element specifies
the base address and size of the alias register region.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the pll parents.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "pll8_vote", "pxo".
- clock-output-names:
Usage: optional
Value type: <string>
Definition: Name of the output clock. Typically acpuX_aux where X is a
CPU number starting at 0.
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
};

44
Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt 100644
View File

@ -0,0 +1,44 @@
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of the following. The generic compatible
"qcom,kpss-gcc" should also be included.
"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: base address and size of the register region
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the pll parents.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "pll8_vote", "pxo".
- clock-output-names:
Usage: required
Value type: <string>
Definition: Name of the output clock. Typically acpu_l2_aux indicating
an L2 cache auxiliary clock.
Example:
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};

19
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
View File

@ -16,11 +16,26 @@ Properties:
- reg:
Usage: required
Value Type: <prop-encoded-array>
Definition: Start address and the the size of the register region.
Definition: The first element specifies the llcc base start address and
the size of the register region. The second element specifies
the llcc broadcast base address and size of the register region.
- reg-names:
Usage: required
Value Type: <stringlist>
Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
- interrupts:
Usage: required
Definition: The interrupt is associated with the llcc edac device.
It's used for llcc cache single and double bit error detection
and reporting.
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0x1100000 0x250000>;
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};

20
Documentation/devicetree/bindings/arm/rockchip.txt
View File

@ -5,6 +5,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "vamrs,ficus", "rockchip,rk3399";
- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
Required root node properties:
- compatible = "vamrs,rock960", "rockchip,rk3399";
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@ -13,6 +17,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "asus,rk3288-tinker", "rockchip,rk3288";
- Asus Tinker board S
Required root node properties:
- compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
- Kylin RK3036 board:
Required root node properties:
- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
@ -59,6 +67,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
- Firefly ROC-RK3399-PC board:
Required root node properties:
- compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@ -160,6 +172,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "pine64,rock64", "rockchip,rk3328";
- Pine64 RockPro64 board:
Required root node properties:
- compatible = "pine64,rockpro64", "rockchip,rk3399";
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@ -168,6 +184,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
- Rockchip PX30 Evaluation board:
Required root node properties:
- compatible = "rockchip,px30-evb", "rockchip,px30";
- Rockchip RV1108 Evaluation board
Required root node properties:
- compatible = "rockchip,rv1108-evb", "rockchip,rv1108";

2
Documentation/devicetree/bindings/arm/scu.txt
View File

@ -22,7 +22,7 @@ References:
Example:
scu@a04100000 {
scu@a0410000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};

16
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -7,6 +7,8 @@ SoCs:
compatible = "renesas,emev2"
- RZ/A1H (R7S72100)
compatible = "renesas,r7s72100"
- RZ/A2 (R7S9210)
compatible = "renesas,r7s9210"
- SH-Mobile AG5 (R8A73A00/SH73A0)
compatible = "renesas,sh73a0"
- R-Mobile APE6 (R8A73A40)
@ -23,6 +25,10 @@ SoCs:
compatible = "renesas,r8a7745"
- RZ/G1C (R8A77470)
compatible = "renesas,r8a77470"
- RZ/G2M (R8A774A1)
compatible = "renesas,r8a774a1"
- RZ/G2E (RA8774C0)
compatible = "renesas,r8a774c0"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
@ -107,6 +113,8 @@ Boards:
compatible = "renesas,lager", "renesas,r8a7790"
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
compatible = "renesas,m3ulcb", "renesas,r8a7796"
- M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
compatible = "renesas,m3nulcb", "renesas,r8a77965"
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
@ -143,12 +151,12 @@ Boards:
compatible = "renesas,wheat", "renesas,r8a7792"
Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
product and revision information. If present, a device node for this register
should be added.
Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
allows to retrieve SoC product and revision information. If present, a device
node for this register should be added.
Required properties:
- compatible: Must be "renesas,prr".
- compatible: Must be "renesas,prr" or "renesas,bsid"
- reg: Base address and length of the register block.

11
Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt → Documentation/devicetree/bindings/arm/syna.txt
View File

@ -1,4 +1,9 @@
Marvell Berlin SoC Family Device Tree Bindings
Synaptics SoC Device Tree Bindings
According to https://www.synaptics.com/company/news/conexant-marvell
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
berlin SoCs are now Synaptics' SoCs now.
---------------------------------------------------------------
Work in progress statement:
@ -13,6 +18,10 @@ stable binding/ABI.
---------------------------------------------------------------
Boards with the Synaptics AS370 SoC shall have the following properties:
Required root node property:
compatible: "syna,as370"
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:

9
Documentation/devicetree/bindings/arm/tegra.txt
View File

@ -47,12 +47,17 @@ board-specific compatible values:
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval
toradex,apalis_t30-v1.1
toradex,apalis_t30-v1.1-eval
toradex,apalis-tk1
toradex,apalis-tk1-eval
toradex,colibri_t20-512
toradex,apalis-tk1-v1.2
toradex,apalis-tk1-v1.2-eval
toradex,colibri_t20
toradex,colibri_t20-eval-v3
toradex,colibri_t20-iris
toradex,colibri_t30
toradex,colibri_t30-eval-v3
toradex,iris
Trusted Foundations
-------------------------------------------

93
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
View File

@ -34,3 +34,96 @@ Board DTS:
pmc@c360000 {
nvidia,invert-interrupt;
};
== Pad Control ==
On Tegra SoCs a pad is a set of pins which are configured as a group.
The pin grouping is a fixed attribute of the hardware. The PMC can be
used to set pad power state and signaling voltage. A pad can be either
in active or power down mode. The support for power state and signaling
voltage configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.
Pad configurations are described with pin configuration nodes which
are placed under the pmc node and they are referred to by the pinctrl
client properties. For more information see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The following pads are present on Tegra186:
csia csib dsi mipi-bias
pex-clk-bias pex-clk3 pex-clk2 pex-clk1
usb0 usb1 usb2 usb-bias
uart audio hsic dbg
hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
sdmmc4 cam dsib dsic
dsid csic csid csie
dsif spi ufs dmic-hv
edp sdmmc1-hv sdmmc3-hv conn
audio-hv ao-hv
Required pin configuration properties:
- pins: A list of strings, each of which contains the name of a pad
to be configured.
Optional pin configuration properties:
- low-power-enable: Configure the pad into power down mode
- low-power-disable: Configure the pad into active mode
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
Note: The power state can be configured on all of the above pads except
for ao-hv. Following pads have software configurable signaling
voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
ao-hv.
Pad configuration state example:
pmc: pmc@7000e400 {
compatible = "nvidia,tegra186-pmc";
reg = <0 0x0c360000 0 0x10000>,
<0 0x0c370000 0 0x10000>,
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
...
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
hdmi_off: hdmi-off {
pins = "hdmi";
low-power-enable;
}
hdmi_on: hdmi-on {
pins = "hdmi";
low-power-disable;
}
};
Pinctrl client example:
sdmmc1: sdhci@3400000 {
...
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
};
...
sor0: sor@15540000 {
...
pinctrl-0 = <&hdmi_off>;
pinctrl-1 = <&hdmi_on>;
pinctrl-names = "hdmi-on", "hdmi-off";
};

103
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
View File

@ -195,3 +195,106 @@ Example:
power-domains = <&pd_audio>;
...
};
== Pad Control ==
On Tegra SoCs a pad is a set of pins which are configured as a group.
The pin grouping is a fixed attribute of the hardware. The PMC can be
used to set pad power state and signaling voltage. A pad can be either
in active or power down mode. The support for power state and signaling
voltage configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.
The pad configuration state nodes are placed under the pmc node and they
are referred to by the pinctrl client properties. For more information
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The pad name should be used as the value of the pins property in pin
configuration nodes.
The following pads are present on Tegra124 and Tegra132:
audio bb cam comp
csia csb cse dsi
dsib dsic dsid hdmi
hsic hv lvds mipi-bias
nand pex-bias pex-clk1 pex-clk2
pex-cntrl sdmmc1 sdmmc3 sdmmc4
sys_ddc uart usb0 usb1
usb2 usb_bias
The following pads are present on Tegra210:
audio audio-hv cam csia
csib csic csid csie
csif dbg debug-nonao dmic
dp dsi dsib dsic
dsid emmc emmc2 gpio
hdmi hsic lvds mipi-bias
pex-bias pex-clk1 pex-clk2 pex-cntrl
sdmmc1 sdmmc3 spi spi-hv
uart usb0 usb1 usb2
usb3 usb-bias
Required pin configuration properties:
- pins: Must contain name of the pad(s) to be configured.
Optional pin configuration properties:
- low-power-enable: Configure the pad into power down mode
- low-power-disable: Configure the pad into active mode
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
Note: The power state can be configured on all of the Tegra124 and
Tegra132 pads. None of the Tegra124 or Tegra132 pads support
signaling voltage switching.
Note: All of the listed Tegra210 pads except pex-cntrl support power
state configuration. Signaling voltage switching is supported on
following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
Pad configuration state example:
pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
...
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
hdmi_off: hdmi-off {
pins = "hdmi";
low-power-enable;
}
hdmi_on: hdmi-on {
pins = "hdmi";
low-power-disable;
}
};
Pinctrl client example:
sdmmc1: sdhci@700b0000 {
...
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
};
...
sor@54540000 {
...
pinctrl-0 = <&hdmi_off>;
pinctrl-1 = <&hdmi_on>;
pinctrl-names = "hdmi-on", "hdmi-off";
};

2
Documentation/devicetree/bindings/arm/ux500/boards.txt
View File

@ -60,7 +60,7 @@ Example:
<0xa0410100 0x100>;
};
scu@a04100000 {
scu@a0410000 {
compatible = "arm,cortex-a9-scu";
reg = <0xa0410000 0x100>;
};

2
Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
View File

@ -13,6 +13,7 @@ Required Properties:
region.
- clocks: Reference to the parent clocks ("hosc", "losc")
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Each clock is assigned an identifier, and client nodes can use this identifier
to specify the clock which they consume.
@ -36,6 +37,7 @@ Example: Clock Management Unit node:
reg = <0x0 0xe0160000 0x0 0x1000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes clock generated by the clock

516
Documentation/devicetree/bindings/clock/at91-clock.txt
View File

@ -4,6 +4,8 @@ This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Slow Clock controller:
Required properties:
- compatible : shall be one of the following:
"atmel,at91sam9x5-sckc" or
@ -16,84 +18,6 @@ Required properties:
"atmel,at91sam9x5-clk-slow-rc-osc":
at91 internal slow RC oscillator
"atmel,<chip>-pmc":
at91 PMC (Power Management Controller)
All at91 specific clocks (clocks defined below) must be child
node of the PMC node.
<chip> can be: at91rm9200, at91sam9260, at91sam9261,
at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5,
sama5d2, sama5d3 or sama5d4.
"atmel,at91sam9x5-clk-slow" (under sckc node)
or
"atmel,at91sam9260-clk-slow" (under pmc node):
at91 slow clk
"atmel,at91rm9200-clk-main-osc"
"atmel,at91sam9x5-clk-main-rc-osc"
at91 main clk sources
"atmel,at91sam9x5-clk-main"
"atmel,at91rm9200-clk-main":
at91 main clock
"atmel,at91rm9200-clk-master" or
"atmel,at91sam9x5-clk-master":
at91 master clock
"atmel,at91sam9x5-clk-peripheral" or
"atmel,at91rm9200-clk-peripheral":
at91 peripheral clocks
"atmel,at91rm9200-clk-pll" or
"atmel,at91sam9g45-clk-pll" or
"atmel,at91sam9g20-clk-pllb" or
"atmel,sama5d3-clk-pll":
at91 pll clocks
"atmel,at91sam9x5-clk-plldiv":
at91 plla divisor
"atmel,at91rm9200-clk-programmable" or
"atmel,at91sam9g45-clk-programmable" or
"atmel,at91sam9x5-clk-programmable":
at91 programmable clocks
"atmel,at91sam9x5-clk-smd":
at91 SMD (Soft Modem) clock
"atmel,at91rm9200-clk-system":
at91 system clocks
"atmel,at91rm9200-clk-usb" or
"atmel,at91sam9x5-clk-usb" or
"atmel,at91sam9n12-clk-usb":
at91 usb clock
"atmel,at91sam9x5-clk-utmi":
at91 utmi clock
"atmel,sama5d4-clk-h32mx":
at91 h32mx clock
"atmel,sama5d2-clk-generated":
at91 generated clock
"atmel,sama5d2-clk-audio-pll-frac":
at91 audio fractional pll
"atmel,sama5d2-clk-audio-pll-pad":
at91 audio pll CLK_AUDIO output pin
"atmel,sama5d2-clk-audio-pll-pmc"
at91 audio pll output on AUDIOPLLCLK that feeds the PMC
and can be used by peripheral clock or generic clock
"atmel,sama5d2-clk-i2s-mux" (under pmc node):
at91 I2S clock source selection
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
@ -109,428 +33,30 @@ For example:
/* put at91 slow clocks here */
};
Power Management Controller (PMC):
Required properties for internal slow RC oscillator:
- #clock-cells : from common clock binding; shall be set to 0.
- clock-frequency : define the internal RC oscillator frequency.
Optional properties:
- clock-accuracy : define the internal RC oscillator accuracy.
For example:
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
clock-frequency = <32768>;
clock-accuracy = <50000000>;
};
Required properties for slow oscillator:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
Required properties:
- compatible : shall be "atmel,<chip>-pmc", "syscon":
<chip> can be: at91rm9200, at91sam9260, at91sam9261,
at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
sama5d2, sama5d3 or sama5d4.
- #clock-cells : from common clock binding; shall be set to 2. The first entry
is the type of the clock (core, system, peripheral or generated) and the
second entry its index as provided by the datasheet
- clocks : Must contain an entry for each entry in clock-names.
- clock-names: Must include the following entries: "slow_clk", "main_xtal"
Optional properties:
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
provided on XIN.
For example:
slow_osc: slow_osc {
compatible = "atmel,at91rm9200-clk-slow-osc";
#clock-cells = <0>;
clocks = <&slow_xtal>;
};
Required properties for slow clock:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the slow clk sources (see atmel datasheet).
For example:
clk32k: slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc &slow_osc>;
};
Required properties for PMC node:
- reg : defines the IO memory reserved for the PMC.
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- interrupts : shall be set to PMC interrupt line.
- interrupt-controller : tell that the PMC is an interrupt controller.
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
and reflect the bit position in the PMC_ER/DR/SR registers.
You can use the dt macros defined in dt-bindings/clock/at91.h.
0 (AT91_PMC_MOSCS) -> main oscillator ready
1 (AT91_PMC_LOCKA) -> PLL A ready
2 (AT91_PMC_LOCKB) -> PLL B ready
3 (AT91_PMC_MCKRDY) -> master clock ready
6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
16 (AT91_PMC_MOSCSELS) -> main oscillator selected
17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
18 (AT91_PMC_CFDEV) -> clock failure detected
For example:
pmc: pmc@fffffc00 {
compatible = "atmel,sama5d3-pmc";
interrupts = <1 4 7>;
interrupt-controller;
#interrupt-cells = <2>;
#size-cells = <0>;
#address-cells = <1>;
/* put at91 clocks here */
};
Required properties for main clock internal RC oscillator:
- interrupts : shall be set to "<0>".
- clock-frequency : define the internal RC oscillator frequency.
Optional properties:
- clock-accuracy : define the internal RC oscillator accuracy.
For example:
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
interrupt-parent = <&pmc>;
interrupts = <0>;
clock-frequency = <12000000>;
clock-accuracy = <50000000>;
};
Required properties for main clock oscillator:
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
Optional properties:
- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
on XIN.
clock signal is directly provided on XIN pin.
For example:
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
interrupt-parent = <&pmc>;
interrupts = <0>;
#clock-cells = <0>;
clocks = <&main_xtal>;
};
Required properties for main clock:
- interrupts : shall be set to "<0>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall encode the main clk sources (see atmel datasheet).
For example:
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
interrupt-parent = <&pmc>;
interrupts = <0>;
#clock-cells = <0>;
clocks = <&main_rc_osc &main_osc>;
};
Required properties for master clock:
- interrupts : shall be set to "<3>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock sources (see atmel datasheet) phandles.
e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
- atmel,clk-output-range : minimum and maximum clock frequency (two u32
fields).
e.g. output = <0 133000000>; <=> 0 to 133MHz.
- atmel,clk-divisors : master clock divisors table (four u32 fields).
0 <=> reserved value.
e.g. divisors = <1 2 4 6>;
- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
PRES field as CLOCK_DIV3 (e.g sam9x5).
For example:
mck: mck {
compatible = "atmel,at91rm9200-clk-master";
interrupt-parent = <&pmc>;
interrupts = <3>;
#clock-cells = <0>;
atmel,clk-output-range = <0 133000000>;
atmel,clk-divisors = <1 2 4 0>;
};
Required properties for peripheral clocks:
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the master clock phandle.
e.g. clocks = <&mck>;
- name: device tree node describing a specific peripheral clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg: peripheral id. See Atmel's datasheets to get a full
list of peripheral ids.
* atmel,clk-output-range : minimum and maximum clock frequency
(two u32 fields). Only valid on at91sam9x5-clk-peripheral
compatible IPs.
For example:
periph: periphck {
compatible = "atmel,at91sam9x5-clk-peripheral";
#size-cells = <0>;
#address-cells = <1>;
clocks = <&mck>;
ssc0_clk {
#clock-cells = <0>;
reg = <2>;
atmel,clk-output-range = <0 133000000>;
};
usart0_clk {
#clock-cells = <0>;
reg = <3>;
atmel,clk-output-range = <0 66000000>;
};
};
Required properties for pll clocks:
- interrupts : shall be set to "<1>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock phandle.
- reg : pll id.
0 -> PLL A
1 -> PLL B
- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
fields).
e.g. input = <1 32000000>; <=> 1 to 32MHz.
- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
range description. Sould be set to 2, 3
or 4.
* 1st and 2nd cells represent the frequency range (min-max).
* 3rd cell is optional and represents the OUT field value for the given
range.
* 4th cell is optional and represents the ICPLL field (PLLICPR
register)
- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
depending on #atmel,pll-output-range-cells
property value.
For example:
plla: pllack {
compatible = "atmel,at91sam9g45-clk-pll";
interrupt-parent = <&pmc>;
interrupts = <1>;
#clock-cells = <0>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <2000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <74500000 800000000 0 0
69500000 750000000 1 0
64500000 700000000 2 0
59500000 650000000 3 0
54500000 600000000 0 1
49500000 550000000 1 1
44500000 500000000 2 1
40000000 450000000 3 1>;
};
Required properties for plldiv clocks (plldiv = pll / 2):
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the plla clock phandle.
The pll divisor is equal to 2 and cannot be changed.
For example:
plladiv: plladivck {
compatible = "atmel,at91sam9x5-clk-plldiv";
#clock-cells = <0>;
clocks = <&plla>;
};
Required properties for programmable clocks:
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the programmable clock source phandles.
e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
- name: device tree node describing a specific prog clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg : programmable clock id (register offset from PCKx
register).
* interrupts : shall be set to "<(8 + id)>".
For example:
prog: progck {
compatible = "atmel,at91sam9g45-clk-programmable";
#size-cells = <0>;
#address-cells = <1>;
interrupt-parent = <&pmc>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
prog0 {
#clock-cells = <0>;
reg = <0>;
interrupts = <8>;
};
prog1 {
#clock-cells = <0>;
reg = <1>;
interrupts = <9>;
};
};
Required properties for smd clock:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the smd clock source phandles.
e.g. clocks = <&plladiv>, <&utmi>;
For example:
smd: smdck {
compatible = "atmel,at91sam9x5-clk-smd";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
Required properties for system clocks:
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- name: device tree node describing a specific system clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg: system clock id (bit position in SCER/SCDR/SCSR registers).
See Atmel's datasheet to get a full list of system clock ids.
For example:
system: systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
ddrck {
#clock-cells = <0>;
reg = <2>;
clocks = <&mck>;
};
uhpck {
#clock-cells = <0>;
reg = <6>;
clocks = <&usb>;
};
udpck {
#clock-cells = <0>;
reg = <7>;
clocks = <&usb>;
};
};
Required properties for usb clock:
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the smd clock source phandles.
e.g. clocks = <&pllb>;
- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
usb clock divisor table.
e.g. divisors = <1 2 4 0>;
For example:
usb: usbck {
compatible = "atmel,at91sam9x5-clk-usb";
#clock-cells = <0>;
clocks = <&plladiv>, <&utmi>;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-usb";
#clock-cells = <0>;
clocks = <&pllb>;
atmel,clk-divisors = <1 2 4 0>;
};
Required properties for utmi clock:
- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the main clock source phandle.
For example:
utmi: utmick {
compatible = "atmel,at91sam9x5-clk-utmi";
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <0>;
clocks = <&main>;
};
Required properties for 32 bits bus Matrix clock (h32mx clock):
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : shall be the master clock source phandle.
For example:
h32ck: h32mxck {
#clock-cells = <0>;
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
};
Required properties for generated clocks:
- #size-cells : shall be 0 (reg is used to encode clk id).
- #address-cells : shall be 1 (reg is used to encode clk id).
- clocks : shall be the generated clock source phandles.
e.g. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
- name: device tree node describing a specific generated clock.
* #clock-cells : from common clock binding; shall be set to 0.
* reg: peripheral id. See Atmel's datasheets to get a full
list of peripheral ids.
* atmel,clk-output-range : minimum and maximum clock frequency
(two u32 fields).
For example:
gck {
compatible = "atmel,sama5d2-clk-generated";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
tcb0_gclk: tcb0_gclk {
#clock-cells = <0>;
reg = <35>;
atmel,clk-output-range = <0 83000000>;
};
pwm_gclk: pwm_gclk {
#clock-cells = <0>;
reg = <38>;
atmel,clk-output-range = <0 83000000>;
};
};
Required properties for I2S mux clocks:
- #size-cells : shall be 0 (reg is used to encode I2S bus id).
- #address-cells : shall be 1 (reg is used to encode I2S bus id).
- name: device tree node describing a specific mux clock.
* #clock-cells : from common clock binding; shall be set to 0.
* clocks : shall be the mux clock parent phandles; shall be 2 phandles:
peripheral and generated clock; the first phandle shall belong to the
peripheral clock and the second one shall belong to the generated
clock; "clock-indices" property can be user to specify
the correct order.
* reg: I2S bus id of the corresponding mux clock.
e.g. reg = <0>; for i2s0, reg = <1>; for i2s1
For example:
i2s_clkmux {
compatible = "atmel,sama5d2-clk-i2s-mux";
#address-cells = <1>;
#size-cells = <0>;
i2s0muxck: i2s0_muxclk {
clocks = <&i2s0_clk>, <&i2s0_gclk>;
#clock-cells = <0>;
reg = <0>;
};
i2s1muxck: i2s1_muxclk {
clocks = <&i2s1_clk>, <&i2s1_gclk>;
#clock-cells = <0>;
reg = <1>;
};
pmc: pmc@f0018000 {
compatible = "atmel,sama5d4-pmc", "syscon";
reg = <0xf0018000 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
#clock-cells = <2>;
clocks = <&clk32k>, <&main_xtal>;
clock-names = "slow_clk", "main_xtal";
};

43
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@ -0,0 +1,43 @@
* Hisilicon Hi3670 Clock Controller
The Hi3670 clock controller generates and supplies clock to various
controllers within the Hi3670 SoC.
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi3670-crgctrl"
- "hisilicon,hi3670-pctrl"
- "hisilicon,hi3670-pmuctrl"
- "hisilicon,hi3670-sctrl"
- "hisilicon,hi3670-iomcu"
- "hisilicon,hi3670-media1-crg"
- "hisilicon,hi3670-media2-crg"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.
Examples:
crg_ctrl: clock-controller@fff35000 {
compatible = "hisilicon,hi3670-crgctrl", "syscon";
reg = <0x0 0xfff35000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
};

8
Documentation/devicetree/bindings/clock/imx6q-clock.txt
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@ -6,6 +6,14 @@ Required properties:
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
Optional properties:
- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
on power off.
Use this property if the SoC should be powered off by external power
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
be using "syscon-poweroff" driver instead.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
for the full list of i.MX6 Quad and DualLite clock IDs.

7
Documentation/devicetree/bindings/clock/ingenic,cgu.txt
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@ -6,8 +6,11 @@ to provide many different clock signals derived from only 2 external source
clocks.
Required properties:
- compatible : Should be "ingenic,<soctype>-cgu".
For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
- compatible : Should be one of:
* ingenic,jz4740-cgu
* ingenic,jz4725b-cgu
* ingenic,jz4770-cgu
* ingenic,jz4780-cgu
- reg : The address & length of the CGU registers.
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
Two such external clocks should be specified - first the external crystal

18
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@ -0,0 +1,18 @@
Qualcomm Camera Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-camcc".
- reg : shall contain base register location and length.
- #clock-cells : from common clock binding, shall contain 1.
- #reset-cells : from common reset binding, shall contain 1.
- #power-domain-cells : from generic power domain binding, shall contain 1.
Example:
camcc: clock-controller@ad00000 {
compatible = "qcom,sdm845-camcc";
reg = <0xad00000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

3
Documentation/devicetree/bindings/clock/qcom,gcc.txt
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@ -19,6 +19,9 @@ Required properties :
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
"qcom,gcc-qcs404"
"qcom,gcc-sdm630"
"qcom,gcc-sdm660"
"qcom,gcc-sdm845"
- reg : shall contain base register location and length

60
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@ -0,0 +1,60 @@
High-Frequency PLL (HFPLL)
PROPERTIES
- compatible:
Usage: required
Value type: <string>:
shall contain only one of the following. The generic
compatible "qcom,hfpll" should be also included.
"qcom,hfpll-ipq8064", "qcom,hfpll"
"qcom,hfpll-apq8064", "qcom,hfpll"
"qcom,hfpll-msm8974", "qcom,hfpll"
"qcom,hfpll-msm8960", "qcom,hfpll"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: address and size of HPLL registers. An optional second
element specifies the address and size of the alias
register region.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the xo clock.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "xo".
- clock-output-names:
Usage: required
Value type: <string>
Definition: Name of the PLL. Typically hfpllX where X is a CPU number
starting at 0. Otherwise hfpll_Y where Y is more specific
such as "l2".
Example:
1) An HFPLL for the L2 cache.
clock-controller@f9016000 {
compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
reg = <0xf9016000 0x30>;
clocks = <&xo_board>;
clock-names = "xo";
clock-output-names = "hfpll_l2";
};
2) An HFPLL for CPU0. This HFPLL has the alias register region.
clock-controller@f908a000 {
compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
clocks = <&xo_board>;
clock-names = "xo";
clock-output-names = "hfpll0";
};

34
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@ -0,0 +1,34 @@
Krait Clock Controller
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,krait-cc-v1"
"qcom,krait-cc-v2"
- #clock-cells:
Usage: required
Value type: <u32>
Definition: must be 1
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the clock parents of hfpll, secondary muxes.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
Example:
kraitcc: clock-controller {
compatible = "qcom,krait-cc-v1";
clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, <qsb>;
clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb";
#clock-cells = <1>;
};

17
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
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@ -13,9 +13,13 @@ They provide the following functionalities:
Required Properties:
- compatible: Must be one of:
- "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
- "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@ -35,12 +39,13 @@ Required Properties:
- clocks: References to external parent clocks, one entry for each entry in
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
r8a77980, r8a77990, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
r8a7794)
- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
r8a77995)
- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
r8a7793, r8a7794)
- #clock-cells: Must be 2
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

73
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@ -0,0 +1,73 @@
==================
C-SKY CPU Bindings
==================
The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.
Only SMP system need to care about the cpus node and single processor
needn't define cpus node at all.
=====================================
cpus and cpu node bindings definition
=====================================
- cpus node
Description: Container of cpu nodes
The node name must be "cpus".
A cpus node must define the following properties:
- #address-cells
Usage: required
Value type: <u32>
Definition: must be set to 1
- #size-cells
Usage: required
Value type: <u32>
Definition: must be set to 0
- cpu node
Description: Describes one of SMP cores
PROPERTIES
- device_type
Usage: required
Value type: <string>
Definition: must be "cpu"
- reg
Usage: required
Value type: <u32>
Definition: CPU index
- compatible:
Usage: required
Value type: <string>
Definition: must contain "csky", eg:
"csky,610"
"csky,807"
"csky,810"
"csky,860"
Example:
--------
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0>;
status = "ok";
};
cpu@1 {
device_type = "cpu";
reg = <1>;
status = "ok";
};
};

23
Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt
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@ -15,6 +15,13 @@ Required children nodes:
to external devices using the OF graph reprensentation (see ../graph.txt).
At least one port node is required.
Optional properties in grandchild nodes:
Any endpoint grandchild node may specify a desired video interface
according to ../../media/video-interfaces.txt, specifically
- bus-width: recognized values are <12>, <16>, <18> and <24>, and
override any output mode selection heuristic, forcing "rgb444",
"rgb565", "rgb666" and "rgb888" respectively.
Example:
hlcdc: hlcdc@f0030000 {
@ -50,3 +57,19 @@ Example:
#pwm-cells = <3>;
};
};
Example 2: With a video interface override to force rgb565; as above
but with these changes/additions:
&hlcdc {
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
port@0 {
hlcdc_panel_output: endpoint@0 {
bus-width = <16>;
};
};
};
};

8
Documentation/devicetree/bindings/display/bridge/lvds-transmitter.txt
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@ -22,7 +22,13 @@ among others.
Required properties:
- compatible: Must be "lvds-encoder"
- compatible: Must be one or more of the following
- "ti,ds90c185" for the TI DS90C185 FPD-Link Serializer
- "lvds-encoder" for a generic LVDS encoder device
When compatible with the generic version, nodes must list the
device-specific version corresponding to the device first
followed by the generic version.
Required nodes:

14
Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt
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@ -14,10 +14,22 @@ Required properties:
- "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
- "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
- "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
- "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders
- "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders
- "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
- reg: Base address and length for the memory-mapped registers
- clocks: A phandle + clock-specifier pair for the functional clock
- clocks: A list of phandles + clock-specifier pairs, one for each entry in
the clock-names property.
- clock-names: Name of the clocks. This property is model-dependent.
- The functional clock, which mandatory for all models, shall be listed
first, and shall be named "fck".
- On R8A77990 and R8A77995, the LVDS encoder can use the EXTAL or
DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
numerical index.
- When the clocks property only contains the functional clock, the
clock-names property may be omitted.
- resets: A phandle + reset specifier for the module reset
Required nodes:

87
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@ -0,0 +1,87 @@
SN65DSI86 DSI to eDP bridge chip
--------------------------------
This is the binding for Texas Instruments SN65DSI86 bridge.
http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
Required properties:
- compatible: Must be "ti,sn65dsi86"
- reg: i2c address of the chip, 0x2d as per datasheet
- enable-gpios: gpio specification for bridge_en pin (active high)
- vccio-supply: A 1.8V supply that powers up the digital IOs.
- vpll-supply: A 1.8V supply that powers up the displayport PLL.
- vcca-supply: A 1.2V supply that powers up the analog circuits.
- vcc-supply: A 1.2V supply that powers up the digital core.
Optional properties:
- interrupts-extended: Specifier for the SN65DSI86 interrupt line.
- gpio-controller: Marks the device has a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify flags.
See ../../gpio/gpio.txt for more information.
- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of
the cell formats.
- clock-names: should be "refclk"
- clocks: Specification for input reference clock. The reference
clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
- data-lanes: See ../../media/video-interface.txt
- lane-polarities: See ../../media/video-interface.txt
- suspend-gpios: specification for GPIO1 pin on bridge (active low)
Required nodes:
This device has two video ports. Their connections are modelled using the
OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 for DSI input
- Video port 1 for eDP output
Example
-------
edp-bridge@2d {
compatible = "ti,sn65dsi86";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2d>;
enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
vccio-supply = <&pm8916_l17>;
vcca-supply = <&pm8916_l6>;
vpll-supply = <&pm8916_l17>;
vcc-supply = <&pm8916_l6>;
clock-names = "refclk";
clocks = <&input_refclk>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_bridge_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
port@1 {
reg = <1>;
edp_bridge_out: endpoint {
data-lanes = <2 1 3 0>;
lane-polarities = <0 1 0 1>;
remote-endpoint = <&edp_panel_in>;
};
};
};
}

35
Documentation/devicetree/bindings/display/bridge/toshiba,tc358764.txt 100644
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@ -0,0 +1,35 @@
TC358764 MIPI-DSI to LVDS panel bridge
Required properties:
- compatible: "toshiba,tc358764"
- reg: the virtual channel number of a DSI peripheral
- vddc-supply: core voltage supply, 1.2V
- vddio-supply: I/O voltage supply, 1.8V or 3.3V
- vddlvds-supply: LVDS1/2 voltage supply, 3.3V
- reset-gpios: a GPIO spec for the reset pin
The device node can contain following 'port' child nodes,
according to the OF graph bindings defined in [1]:
0: DSI Input, not required, if the bridge is DSI controlled
1: LVDS Output, mandatory
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
bridge@0 {
reg = <0>;
compatible = "toshiba,tc358764";
vddc-supply = <&vcc_1v2_reg>;
vddio-supply = <&vcc_1v8_reg>;
vddlvds-supply = <&vcc_3v3_reg>;
reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
lvds_ep: endpoint {
remote-endpoint = <&panel_ep>;
};
};
};

25
Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
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@ -21,6 +21,9 @@ Required properties:
- samsung,pll-clock-frequency: specifies frequency of the oscillator clock
- #address-cells, #size-cells: should be set respectively to <1> and <0>
according to DSI host bindings (see MIPI DSI bindings [1])
- samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
mode
- samsung,esc-clock-frequency: specifies DSI frequency in escape mode
Optional properties:
- power-domains: a phandle to DSIM power domain node
@ -29,25 +32,9 @@ Child nodes:
Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
Video interfaces:
Device node can contain video interface port nodes according to [2].
The following are properties specific to those nodes:
port node inbound:
- reg: (required) must be 0.
port node outbound:
- reg: (required) must be 1.
endpoint node connected from mic node (reg = 0):
- remote-endpoint: specifies the endpoint in mic node. This node is required
for Exynos5433 mipi dsi. So mic can access to panel node
throughout this dsi node.
endpoint node connected to panel node (reg = 1):
- remote-endpoint: specifies the endpoint in panel node. This node is
required in all kinds of exynos mipi dsi to represent
the connection between mipi dsi and panel.
- samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
mode
- samsung,esc-clock-frequency: specifies DSI frequency in escape mode
Device node can contain following video interface port nodes according to [2]:
0: RGB input,
1: DSI output
[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt

153
Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
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@ -16,7 +16,7 @@ The following assumes that only a single peripheral is connected to a DSI
host. Experience shows that this is true for the large majority of setups.
DSI host
--------
========
In addition to the standard properties and those defined by the parent bus of
a DSI host, the following properties apply to a node representing a DSI host.
@ -29,12 +29,24 @@ Required properties:
- #size-cells: Should be 0. There are cases where it makes sense to use a
different value here. See below.
DSI peripheral
--------------
Optional properties:
- clock-master: boolean. Should be enabled if the host is being used in
conjunction with another DSI host to drive the same peripheral. Hardware
supporting such a configuration generally requires the data on both the busses
to be driven by the same clock. Only the DSI host instance controlling this
clock should contain this property.
Peripherals are represented as child nodes of the DSI host's node. Properties
described here apply to all DSI peripherals, but individual bindings may want
to define additional, device-specific properties.
DSI peripheral
==============
Peripherals with DSI as control bus, or no control bus
------------------------------------------------------
Peripherals with the DSI bus as the primary control bus, or peripherals with
no control bus but use the DSI bus to transmit pixel data are represented
as child nodes of the DSI host's node. Properties described here apply to all
DSI peripherals, but individual bindings may want to define additional,
device-specific properties.
Required properties:
- reg: The virtual channel number of a DSI peripheral. Must be in the range
@ -49,9 +61,37 @@ case two alternative representations can be chosen:
property is the number of the first virtual channel and the second cell is
the number of consecutive virtual channels.
Example
-------
Peripherals with a different control bus
----------------------------------------
There are peripherals that have I2C/SPI (or some other non-DSI bus) as the
primary control bus, but are also connected to a DSI bus (mostly for the data
path). Connections between such peripherals and a DSI host can be represented
using the graph bindings [1], [2].
Peripherals that support dual channel DSI
-----------------------------------------
Peripherals with higher bandwidth requirements can be connected to 2 DSI
busses. Each DSI bus/channel drives some portion of the pixel data (generally
left/right half of each line of the display, or even/odd lines of the display).
The graph bindings should be used to represent the multiple DSI busses that are
connected to this peripheral. Each DSI host's output endpoint can be linked to
an input endpoint of the DSI peripheral.
[1] Documentation/devicetree/bindings/graph.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
Examples
========
- (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
with different virtual channel configurations.
- (4) is an example of a peripheral on a I2C control bus connected to a
DSI host using of-graph bindings.
- (5) is an example of 2 DSI hosts driving a dual-channel DSI peripheral,
which uses I2C as its primary control bus.
1)
dsi-host {
...
@ -67,6 +107,7 @@ Example
...
};
2)
dsi-host {
...
@ -82,6 +123,7 @@ Example
...
};
3)
dsi-host {
...
@ -96,3 +138,98 @@ Example
...
};
4)
i2c-host {
...
dsi-bridge@35 {
compatible = "...";
reg = <0x35>;
ports {
...
port {
bridge_mipi_in: endpoint {
remote-endpoint = <&host_mipi_out>;
};
};
};
};
};
dsi-host {
...
ports {
...
port {
host_mipi_out: endpoint {
remote-endpoint = <&bridge_mipi_in>;
};
};
};
};
5)
i2c-host {
dsi-bridge@35 {
compatible = "...";
reg = <0x35>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
dsi1_in: endpoint {
remote-endpoint = <&dsi1_out>;
};
};
};
};
};
dsi0-host {
...
/*
* this DSI instance drives the clock for both the host
* controllers
*/
clock-master;
ports {
...
port {
dsi0_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi1-host {
...
ports {
...
port {
dsi1_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};

4
Documentation/devicetree/bindings/display/renesas,du.txt
View File

@ -15,6 +15,8 @@ Required Properties:
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
- "renesas,du-r8a77965" for R8A77965 (R-Car M3-N) compatible DU
- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
- "renesas,du-r8a77980" for R8A77980 (R-Car V3H) compatible DU
- "renesas,du-r8a77990" for R8A77990 (R-Car E3) compatible DU
- "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
- reg: the memory-mapped I/O registers base address and length
@ -61,6 +63,8 @@ corresponding to each DU output.
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
R8A77965 (R-Car M3-N) DPAD 0 HDMI 0 LVDS 0 -
R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
R8A77980 (R-Car V3H) DPAD 0 LVDS 0 - -
R8A77990 (R-Car E3) DPAD 0 LVDS 0 LVDS 1 -
R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -

3
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
View File

@ -8,6 +8,9 @@ Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3126-vop";
"rockchip,px30-vop-lit";
"rockchip,px30-vop-big";
"rockchip,rk3188-vop";
"rockchip,rk3288-vop";
"rockchip,rk3368-vop";
"rockchip,rk3366-vop";

16
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
View File

@ -78,6 +78,7 @@ Required properties:
- compatible: value must be one of:
* "allwinner,sun8i-a83t-dw-hdmi"
* "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"
- reg: base address and size of memory-mapped region
- reg-io-width: See dw_hdmi.txt. Shall be 1.
- interrupts: HDMI interrupt number
@ -96,6 +97,9 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
Optional properties:
- hvcc-supply: the VCC power supply of the controller
DWC HDMI PHY
------------
@ -103,6 +107,7 @@ Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
* allwinner,sun8i-r40-hdmi-phy
* allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
@ -112,9 +117,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
H3 and A64 HDMI PHY require additional clocks:
H3, A64 and R40 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
- pll-1: second possible phy clock parent (A64 only)
- pll-1: second possible phy clock parent (A64/R40 only)
TV Encoder
----------
@ -151,6 +156,8 @@ Required properties:
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
* "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd"
* "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON.
@ -369,7 +376,11 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-0
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-r40-de2-mixer-0
* allwinner,sun8i-r40-de2-mixer-1
* allwinner,sun8i-v3s-de2-mixer
* allwinner,sun50i-a64-de2-mixer-0
* allwinner,sun50i-a64-de2-mixer-1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@ -403,6 +414,7 @@ Required properties:
* allwinner,sun8i-r40-display-engine
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
* allwinner,sun50i-a64-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.

33
Documentation/devicetree/bindings/firmware/qcom,scm.txt
View File

@ -7,16 +7,23 @@ assorted actions.
Required properties:
- compatible: must contain one of the following:
* "qcom,scm-apq8064" for APQ8064 platforms
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms
* "qcom,scm-ipq4019" for IPQ4019 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
* No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
* "qcom,scm-apq8064"
* "qcom,scm-apq8084"
* "qcom,scm-msm8660"
* "qcom,scm-msm8916"
* "qcom,scm-msm8960"
* "qcom,scm-msm8974"
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
* "qcom,scm-ipq4019"
* "qcom,scm-sdm845"
and:
* "qcom,scm"
- clocks: Specifies clocks needed by the SCM interface, if any:
* core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
"qcom,scm-msm8960"
* core, iface and bus clocks required for "qcom,scm-apq8084",
"qcom,scm-msm8916" and "qcom,scm-msm8974"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
clock and "bus" for the bus clock per the requirements of the compatible.
- qcom,dload-mode: phandle to the TCSR hardware block and offset of the
@ -26,8 +33,10 @@ Example for MSM8916:
firmware {
scm {
compatible = "qcom,scm";
clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
compatible = "qcom,msm8916", "qcom,scm";
clocks = <&gcc GCC_CRYPTO_CLK> ,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
};

82
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt 100644
View File

@ -0,0 +1,82 @@
-----------------------------------------------------------------
Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
-----------------------------------------------------------------
The zynqmp-firmware node describes the interface to platform firmware.
ZynqMP has an interface to communicate with secure firmware. Firmware
driver provides an interface to firmware APIs. Interface APIs can be
used by any driver to communicate to PMUFW(Platform Management Unit).
These requests include clock management, pin control, device control,
power management service, FPGA service and other platform management
services.
Required properties:
- compatible: Must contain: "xlnx,zynqmp-firmware"
- method: The method of calling the PM-API firmware layer.
Permitted values are:
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
--------------------------------------------------------------------------
Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
Zynq MPSoC firmware interface
--------------------------------------------------------------------------
The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
tree. It reads required input clock frequencies from the devicetree and acts
as clock provider for all clock consumers of PS clocks.
See clock_bindings.txt for more information on the generic clock bindings.
Required properties:
- #clock-cells: Must be 1
- compatible: Must contain: "xlnx,zynqmp-clk"
- clocks: List of clock specifiers which are external input
clocks to the given clock controller. Please refer
the next section to find the input clocks for a
given controller.
- clock-names: List of clock names which are exteral input clocks
to the given clock controller. Please refer to the
clock bindings for more details.
Input clocks for zynqmp Ultrascale+ clock controller:
The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
inputs. These required clock inputs are:
- pss_ref_clk (PS reference clock)
- video_clk (reference clock for video system )
- pss_alt_ref_clk (alternative PS reference clock)
- aux_ref_clk
- gt_crx_ref_clk (transceiver reference clock)
The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source:
- swdt0_ext_clk
- swdt1_ext_clk
- gem0_emio_clk
- gem1_emio_clk
- gem2_emio_clk
- gem3_emio_clk
- mio_clk_XX # with XX = 00..77
- mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51
Output clocks are registered based on clock information received
from firmware. Output clocks indexes are mentioned in
include/dt-bindings/clock/xlnx,zynqmp-clk.h.
-------
Example
-------
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
};
};

7
Documentation/devicetree/bindings/i2c/i2c-designware.txt
View File

@ -3,6 +3,7 @@
Required properties :
- compatible : should be "snps,designware-i2c"
or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
- reg : Offset and length of the register set for the device
- interrupts : <IRQ> where IRQ is the interrupt number.
@ -11,8 +12,12 @@ Recommended properties :
- clock-frequency : desired I2C bus clock frequency in Hz.
Optional properties :
- reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
time, named ICPU_CFG:TWI_DELAY in the datasheet.
- i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
This option is only supported in hardware blocks version 1.11a or newer.
This option is only supported in hardware blocks version 1.11a or newer and
on Microsemi SoCs ("mscc,ocelot-i2c" compatible).
- i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
This value which is by default 300ns is used to compute the tLOW period.

2
Documentation/devicetree/bindings/i2c/i2c-rcar.txt
View File

@ -3,7 +3,9 @@ I2C for R-Car platforms
Required properties:
- compatible:
"renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
"renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC.
"renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
"renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC.
"renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.

1
Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
View File

@ -5,6 +5,7 @@ Required properties:
- "renesas,iic-r8a73a4" (R-Mobile APE6)
- "renesas,iic-r8a7740" (R-Mobile A1)
- "renesas,iic-r8a7743" (RZ/G1M)
- "renesas,iic-r8a7744" (RZ/G1N)
- "renesas,iic-r8a7745" (RZ/G1E)
- "renesas,iic-r8a774a1" (RZ/G2M)
- "renesas,iic-r8a7790" (R-Car H2)

33
Documentation/devicetree/bindings/iio/accel/adxl372.txt 100644
View File

@ -0,0 +1,33 @@
Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer
http://www.analog.com/media/en/technical-documentation/data-sheets/adxl372.pdf
Required properties:
- compatible : should be "adi,adxl372"
- reg: the I2C address or SPI chip select number for the device
Required properties for SPI bus usage:
- spi-max-frequency: Max SPI frequency to use
Optional properties:
- interrupts: interrupt mapping for IRQ as documented in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example for a I2C device node:
accelerometer@53 {
compatible = "adi,adxl372";
reg = <0x53>;
interrupt-parent = <&gpio>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};
Example for a SPI device node:
accelerometer@0 {
compatible = "adi,adxl372";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&gpio>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
};

30
Documentation/devicetree/bindings/iio/adc/mcp3911.txt 100644
View File

@ -0,0 +1,30 @@
* Microchip MCP3911 Dual channel analog front end (ADC)
Required properties:
- compatible: Should be "microchip,mcp3911"
- reg: SPI chip select number for the device
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt.
Max frequency for this chip is 20MHz.
Optional properties:
- clocks: Phandle and clock identifier for sampling clock
- interrupt-parent: Phandle to the parent interrupt controller
- interrupts: IRQ line for the ADC
- microchip,device-addr: Device address when multiple MCP3911 chips are present on the
same SPI bus. Valid values are 0-3. Defaults to 0.
- vref-supply: Phandle to the external reference voltage supply.
Example:
adc@0 {
compatible = "microchip,mcp3911";
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <15 IRQ_TYPE_EDGE_RISING>;
spi-max-frequency = <20000000>;
microchip,device-addr = <0>;
vref-supply = <&vref_reg>;
clocks = <&xtal>;
};

81
Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
View File

@ -1,7 +1,9 @@
Qualcomm's SPMI PMIC voltage ADC
Qualcomm's SPMI PMIC ADC
SPMI PMIC voltage ADC (VADC) provides interface to clients to read
voltage. The VADC is a 15-bit sigma-delta ADC.
- SPMI PMIC voltage ADC (VADC) provides interface to clients to read
voltage. The VADC is a 15-bit sigma-delta ADC.
- SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read
voltage. The VADC is a 16-bit sigma-delta ADC.
VADC node:
@ -9,11 +11,13 @@ VADC node:
Usage: required
Value type: <string>
Definition: Should contain "qcom,spmi-vadc".
Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.
Should contain "qcom,spmi-adc-rev2" for PMIC rev2 ADC driver.
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: VADC base address and length in the SPMI PMIC register map.
Definition: VADC base address in the SPMI PMIC register map.
- #address-cells:
Usage: required
@ -45,13 +49,26 @@ Channel node properties:
Definition: ADC channel number.
See include/dt-bindings/iio/qcom,spmi-vadc.h
- label:
Usage: required for "qcom,spmi-adc5" and "qcom,spmi-adc-rev2"
Value type: <empty>
Definition: ADC input of the platform as seen in the schematics.
For thermistor inputs connected to generic AMUX or GPIO inputs
these can vary across platform for the same pins. Hence select
the platform schematics name for this channel.
- qcom,decimation:
Usage: optional
Value type: <u32>
Definition: This parameter is used to decrease ADC sampling rate.
Quicker measurements can be made by reducing decimation ratio.
Valid values are 512, 1024, 2048, 4096.
If property is not found, default value of 512 will be used.
- For compatible property "qcom,spmi-vadc", valid values are
512, 1024, 2048, 4096. If property is not found, default value
of 512 will be used.
- For compatible property "qcom,spmi-adc5", valid values are 250, 420
and 840. If property is not found, default value of 840 is used.
- For compatible property "qcom,spmi-adc-rev2", valid values are 256,
512 and 1024. If property is not present, default value is 1024.
- qcom,pre-scaling:
Usage: optional
@ -66,21 +83,38 @@ Channel node properties:
- qcom,ratiometric:
Usage: optional
Value type: <empty>
Definition: Channel calibration type. If this property is specified
VADC will use the VDD reference (1.8V) and GND for channel
calibration. If property is not found, channel will be
calibrated with 0.625V and 1.25V reference channels, also
known as absolute calibration.
Definition: Channel calibration type.
- For compatible property "qcom,spmi-vadc", if this property is
specified VADC will use the VDD reference (1.8V) and GND for
channel calibration. If property is not found, channel will be
calibrated with 0.625V and 1.25V reference channels, also
known as absolute calibration.
- For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2",
if this property is specified VADC will use the VDD reference
(1.875V) and GND for channel calibration. If property is not found,
channel will be calibrated with 0V and 1.25V reference channels,
also known as absolute calibration.
- qcom,hw-settle-time:
Usage: optional
Value type: <u32>
Definition: Time between AMUX getting configured and the ADC starting
conversion. Delay = 100us * (value) for value < 11, and
2ms * (value - 10) otherwise.
Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
900 us and 1, 2, 4, 6, 8, 10 ms
If property is not found, channel will use 0us.
conversion. The 'hw_settle_time' is an index used from valid values
and programmed in hardware to achieve the hardware settling delay.
- For compatible property "qcom,spmi-vadc" and "qcom,spmi-adc-rev2",
Delay = 100us * (hw_settle_time) for hw_settle_time < 11,
and 2ms * (hw_settle_time - 10) otherwise.
Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
900 us and 1, 2, 4, 6, 8, 10 ms.
If property is not found, channel will use 0us.
- For compatible property "qcom,spmi-adc5", delay = 15us for
value 0, 100us * (value) for values < 11,
and 2ms * (value - 10) otherwise.
Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800,
900 us and 1, 2, 4, 6, 8, 10 ms
Certain controller digital versions have valid values of
15, 100, 200, 300, 400, 500, 600, 700, 1, 2, 4, 8, 16, 32, 64, 128 ms
If property is not found, channel will use 15us.
- qcom,avg-samples:
Usage: optional
@ -89,13 +123,18 @@ Channel node properties:
Averaging provides the option to obtain a single measurement
from the ADC that is an average of multiple samples. The value
selected is 2^(value).
Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
If property is not found, 1 sample will be used.
- For compatible property "qcom,spmi-vadc", valid values
are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
If property is not found, 1 sample will be used.
- For compatible property "qcom,spmi-adc5" and "qcom,spmi-adc-rev2",
valid values are: 1, 2, 4, 8, 16
If property is not found, 1 sample will be used.
NOTE:
Following channels, also known as reference point channels, are used for
result calibration and their channel configuration nodes should be defined:
For compatible property "qcom,spmi-vadc" following channels, also known as
reference point channels, are used for result calibration and their channel
configuration nodes should be defined:
VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV,
VADC_GND_REF and VADC_VDD_VADC.
@ -104,7 +143,7 @@ Example:
/* VADC node */
pmic_vadc: vadc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100 0x100>;
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;

4
Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt
View File

@ -12,6 +12,8 @@ Required properties:
- interrupts: The interrupt number for the ADC device.
- #io-channel-cells: Number of cells in an IIO specifier.
- hwlocks: Reference to a phandle of a hwlock provider node.
- nvmem-cells: A phandle to the calibration cells provided by eFuse device.
- nvmem-cell-names: Should be "big_scale_calib", "small_scale_calib".
Example:
@ -32,5 +34,7 @@ Example:
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
hwlocks = <&hwlock 4>;
nvmem-cells = <&adc_big_scale>, <&adc_small_scale>;
nvmem-cell-names = "big_scale_calib", "small_scale_calib";
};
};

5
Documentation/devicetree/bindings/iio/dac/ad5758.txt
View File

@ -50,6 +50,9 @@ Required properties:
Optional properties:
- reset-gpios : GPIO spec for the RESET pin. If specified, it will be
asserted during driver probe.
- adi,dc-dc-ilim-microamp: The dc-to-dc converter current limit
The following values are currently supported [uA]:
* 150000
@ -71,6 +74,8 @@ AD5758 Example:
spi-max-frequency = <1000000>;
spi-cpha;
reset-gpios = <&gpio 22 0>;
adi,dc-dc-mode = <2>;
adi,range-microvolt = <0 10000000>;
adi,dc-dc-ilim-microamp = <200000>;

21
Documentation/devicetree/bindings/iio/dac/ltc1660.txt 100644
View File

@ -0,0 +1,21 @@
* Linear Technology Micropower octal 8-Bit and 10-Bit DACs
Required properties:
- compatible: Must be one of the following:
"lltc,ltc1660"
"lltc,ltc1665"
- reg: SPI chip select number for the device
- vref-supply: Phandle to the voltage reference supply
Recommended properties:
- spi-max-frequency: Definition as per
Documentation/devicetree/bindings/spi/spi-bus.txt.
Max frequency for this chip is 5 MHz.
Example:
dac@0 {
compatible = "lltc,ltc1660";
reg = <0>;
spi-max-frequency = <5000000>;
vref-supply = <&vref_reg>;
};

1
Documentation/devicetree/bindings/iio/imu/inv_mpu6050.txt
View File

@ -20,6 +20,7 @@ Required properties:
bindings.
Optional properties:
- vddio-supply: regulator phandle for VDDIO supply
- mount-matrix: an optional 3x3 mounting rotation matrix
- i2c-gate node. These devices also support an auxiliary i2c bus. This is
simple enough to be described using the i2c-gate binding. See

1
Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
View File

@ -7,6 +7,7 @@ Required properties:
"st,lsm6dsl"
"st,lsm6dsm"
"st,ism330dlc"
"st,lsm6dso"
- reg: i2c address of the sensor / spi cs line
Optional properties:

18
Documentation/devicetree/bindings/iio/light/bh1750.txt 100644
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@ -0,0 +1,18 @@
ROHM BH1750 - ALS, Ambient light sensor
Required properties:
- compatible: Must be one of:
"rohm,bh1710"
"rohm,bh1715"
"rohm,bh1721"
"rohm,bh1750"
"rohm,bh1751"
- reg: the I2C address of the sensor
Example:
light-sensor@23 {
compatible = "rohm,bh1750";
reg = <0x23>;
};

42
Documentation/devicetree/bindings/iio/light/tsl2772.txt 100644
View File

@ -0,0 +1,42 @@
* AMS/TAOS ALS and proximity sensor
Required properties:
- compatible: Should be one of
"amstaos,tsl2571"
"amstaos,tsl2671"
"amstaos,tmd2671"
"amstaos,tsl2771"
"amstaos,tmd2771"
"amstaos,tsl2572"
"amstaos,tsl2672"
"amstaos,tmd2672"
"amstaos,tsl2772"
"amstaos,tmd2772"
"avago,apds9930"
- reg: the I2C address of the device
Optional properties:
- amstaos,proximity-diodes - proximity diodes to enable. <0>, <1>, or <0 1>
are the only valid values.
- led-max-microamp - current for the proximity LED. Must be 100000, 50000,
25000, or 13000.
- vdd-supply: phandle to the regulator that provides power to the sensor.
- vddio-supply: phandle to the regulator that provides power to the bus.
- interrupts: the sole interrupt generated by the device
Refer to interrupt-controller/interrupts.txt for generic interrupt client
node bindings.
Example:
tsl2772@39 {
compatible = "amstaos,tsl2772";
reg = <0x39>;
interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
vdd-supply = <&pm8941_l17>;
vddio-supply = <&pm8941_lvs1>;
amstaos,proximity-diodes = <0>;
led-max-microamp = <100000>;
};

12
Documentation/devicetree/bindings/iio/proximity/vl53l0x.txt 100644
View File

@ -0,0 +1,12 @@
ST VL53L0X ToF ranging sensor
Required properties:
- compatible: must be "st,vl53l0x"
- reg: i2c address where to find the device
Example:
vl53l0x@29 {
compatible = "st,vl53l0x";
reg = <0x29>;
};

4
Documentation/devicetree/bindings/input/pwm-vibrator.txt
View File

@ -58,8 +58,8 @@ Example from Motorola Droid 4:
vibrator {
compatible = "pwm-vibrator";
pwms = <&pwm8 0 1000000000 0>,
<&pwm9 0 1000000000 0>;
pwms = <&pwm9 0 1000000000 0>,
<&pwm8 0 1000000000 0>;
pwm-names = "enable", "direction";
direction-duty-cycle-ns = <1000000000>;
};

6
Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
View File

@ -1,10 +1,12 @@
General Touchscreen Properties:
Optional properties for Touchscreens:
- touchscreen-min-x : minimum x coordinate reported (0 if not set)
- touchscreen-min-y : minimum y coordinate reported (0 if not set)
- touchscreen-size-x : horizontal resolution of touchscreen
(in pixels)
(maximum x coordinate reported + 1)
- touchscreen-size-y : vertical resolution of touchscreen
(in pixels)
(maximum y coordinate reported + 1)
- touchscreen-max-pressure : maximum reported pressure (arbitrary range
dependent on the controller)
- touchscreen-min-pressure : minimum pressure on the touchscreen to be

62
Documentation/devicetree/bindings/interrupt-controller/csky,apb-intc.txt 100644
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@ -0,0 +1,62 @@
==============================
C-SKY APB Interrupt Controller
==============================
C-SKY APB Interrupt Controller is a simple soc interrupt controller
on the apb bus and we only use it as root irq controller.
- csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
- csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
- csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
=============================
intc node bindings definition
=============================
Description: Describes APB interrupt controller
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,apb-intc"
"csky,dual-apb-intc"
"csky,gx6605s-intc"
- #interrupt-cells
Usage: required
Value type: <u32>
Definition: must be <1>
- reg
Usage: required
Value type: <u32 u32>
Definition: <phyaddr size> in soc from cpu view
- interrupt-controller:
Usage: required
- csky,support-pulse-signal:
Usage: select
Description: to support pulse signal flag
Examples:
---------
intc: interrupt-controller@500000 {
compatible = "csky,apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};
intc: interrupt-controller@500000 {
compatible = "csky,dual-apb-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};
intc: interrupt-controller@500000 {
compatible = "csky,gx6605s-intc";
#interrupt-cells = <1>;
reg = <0x00500000 0x400>;
interrupt-controller;
};

40
Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt 100644
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@ -0,0 +1,40 @@
===========================================
C-SKY Multi-processors Interrupt Controller
===========================================
C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
SMP soc, and it also could be used in non-SMP system.
Interrupt number definition:
0-15 : software irq, and we use 15 as our IPI_IRQ.
16-31 : private irq, and we use 16 as the co-processor timer.
31-1024: common irq for soc ip.
=============================
intc node bindings definition
=============================
Description: Describes SMP interrupt controller
PROPERTIES
- compatible
Usage: required
Value type: <string>
Definition: must be "csky,mpintc"
- #interrupt-cells
Usage: required
Value type: <u32>
Definition: must be <1>
- interrupt-controller:
Usage: required
Examples:
---------
intc: interrupt-controller {
compatible = "csky,mpintc";
#interrupt-cells = <1>;
interrupt-controller;
};

4
Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
View File

@ -41,6 +41,8 @@ Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
generation one m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
@ -51,7 +53,7 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701,
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
dt-binding/memory/mt2712-larb-port.h for mt2712, and
dt-binding/memory/mt8173-larb-port.h for mt8173.

1
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
View File

@ -11,6 +11,7 @@ platforms.
"qcom,msm8916-apcs-kpss-global",
"qcom,msm8996-apcs-hmss-global"
"qcom,msm8998-apcs-hmss-global"
"qcom,qcs404-apcs-apps-global"
"qcom,sdm845-apss-shared"
- reg:

54
Documentation/devicetree/bindings/media/cedrus.txt 100644
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@ -0,0 +1,54 @@
Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the
Video Engine (VE) in Allwinner literature.
The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting
from the DRAM base. This requires specific memory allocation and handling.
Required properties:
- compatible : must be one of the following compatibles:
- "allwinner,sun4i-a10-video-engine"
- "allwinner,sun5i-a13-video-engine"
- "allwinner,sun7i-a20-video-engine"
- "allwinner,sun8i-a33-video-engine"
- "allwinner,sun8i-h3-video-engine"
- reg : register base and length of VE;
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property;
- clock-names : should contain "ahb", "mod" and "ram" entries;
- resets : phandle for reset;
- interrupts : VE interrupt number;
- allwinner,sram : SRAM region to use with the VE.
Optional properties:
- memory-region : CMA pool to use for buffers allocation instead of the
default CMA pool.
Example:
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
cma_pool: cma@4a000000 {
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x4a000000 0x6000000>;
reusable;
linux,cma-default;
};
};
video-codec@1c0e000 {
compatible = "allwinner,sun7i-a20-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
allwinner,sram = <&ve_sram 1>;
};

26
Documentation/devicetree/bindings/media/fsl-pxp.txt 100644
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@ -0,0 +1,26 @@
Freescale Pixel Pipeline
========================
The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
that supports scaling, colorspace conversion, alpha blending, rotation, and
pixel conversion via lookup table. Different versions are present on various
i.MX SoCs from i.MX23 to i.MX7.
Required properties:
- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
imx6dl, imx6sl, imx6ul, imx6sx, imx6ull, or imx7d.
- reg: the register base and size for the device registers
- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
- clock-names: should be "axi"
- clocks: the PXP AXI clock
Example:
pxp@21cc000 {
compatible = "fsl,imx6ull-pxp";
reg = <0x021cc000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "axi";
clocks = <&clks IMX6UL_CLK_PXP>;
};

20
Documentation/devicetree/bindings/media/i2c/adv748x.txt
View File

@ -10,7 +10,11 @@ Required Properties:
- "adi,adv7481" for the ADV7481
- "adi,adv7482" for the ADV7482
- reg: I2C slave address
- reg: I2C slave addresses
The ADV748x has up to twelve 256-byte maps that can be accessed via the
main I2C ports. Each map has it own I2C address and acts as a standard
slave device on the I2C bus. The main address is mandatory, others are
optional and remain at default values if not specified.
Optional Properties:
@ -18,6 +22,11 @@ Optional Properties:
"intrq3". All interrupts are optional. The "intrq3" interrupt
is only available on the adv7481
- interrupts: Specify the interrupt lines for the ADV748x
- reg-names : Names of maps with programmable addresses.
It shall contain all maps needing a non-default address.
Possible map names are:
"main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb"
The device node must contain one 'port' child node per device input and output
port, in accordance with the video interface bindings defined in
@ -47,7 +56,10 @@ Example:
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
reg = <0x70 0x71 0x72 0x73 0x74 0x75
0x60 0x61 0x62 0x63 0x64 0x65>;
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
"infoframe", "cbus", "cec", "sdp", "txa", "txb";
#address-cells = <1>;
#size-cells = <0>;
@ -73,7 +85,7 @@ Example:
};
};
port@10 {
port@a {
reg = <10>;
adv7482_txa: endpoint {
@ -83,7 +95,7 @@ Example:
};
};
port@11 {
port@b {
reg = <11>;
adv7482_txb: endpoint {

2
Documentation/devicetree/bindings/media/i2c/adv7604.txt
View File

@ -66,7 +66,7 @@ Example:
* other maps will retain their default addresses.
*/
reg = <0x4c>, <0x66>;
reg-names "main", "edid";
reg-names = "main", "edid";
reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;

0
Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807.txt → Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.txt
View File

1
Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
View File

@ -5,6 +5,7 @@ Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
Required properties:
- compatible : must be one of the following string:
"mediatek,mt8173-jpgdec"
"mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
"mediatek,mt2701-jpgdec"
- reg : physical base address of the jpeg decoder registers and length of
memory mapped region.

1
Documentation/devicetree/bindings/media/rcar_vin.txt
View File

@ -11,6 +11,7 @@ on Gen3 platforms to a CSI-2 receiver.
- compatible: Must be one or more of the following
- "renesas,vin-r8a7743" for the R8A7743 device
- "renesas,vin-r8a7744" for the R8A7744 device
- "renesas,vin-r8a7745" for the R8A7745 device
- "renesas,vin-r8a7778" for the R8A7778 device
- "renesas,vin-r8a7779" for the R8A7779 device

14
Documentation/devicetree/bindings/media/renesas,ceu.txt
View File

@ -17,15 +17,19 @@ Required properties:
The CEU supports a single parallel input and should contain a single 'port'
subnode with a single 'endpoint'. Connection to input devices are modeled
according to the video interfaces OF bindings specified in:
Documentation/devicetree/bindings/media/video-interfaces.txt
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
Optional endpoint properties applicable to parallel input bus described in
the above mentioned "video-interfaces.txt" file are supported.
- hsync-active: Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
If property is not present, default is active high.
- vsync-active: Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
If property is not present, default is active high.
- hsync-active: See [1] for description. If property is not present,
default is active high.
- vsync-active: See [1] for description. If property is not present,
default is active high.
- bus-width: See [1] for description. Accepted values are '8' and '16'.
If property is not present, default is '8'.
- field-even-active: See [1] for description. If property is not present,
an even field is identified by a logic 0 (active-low signal).
Example:

29
Documentation/devicetree/bindings/media/rockchip-vpu.txt 100644
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@ -0,0 +1,29 @@
device-tree bindings for rockchip VPU codec
Rockchip (Video Processing Unit) present in various Rockchip platforms,
such as RK3288 and RK3399.
Required properties:
- compatible: value should be one of the following
"rockchip,rk3288-vpu";
"rockchip,rk3399-vpu";
- interrupts: encoding and decoding interrupt specifiers
- interrupt-names: should be "vepu" and "vdpu"
- clocks: phandle to VPU aclk, hclk clocks
- clock-names: should be "aclk" and "hclk"
- power-domains: phandle to power domain node
- iommus: phandle to a iommu node
Example:
SoC-specific DT entry:
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIDEO>;
iommus = <&vpu_mmu>;
};

4
Documentation/devicetree/bindings/media/video-interfaces.txt
View File

@ -100,10 +100,12 @@ Optional endpoint properties
slave device (data source) by the master device (data sink). In the master
mode the data source device is also the source of the synchronization signals.
- bus-type: data bus type. Possible values are:
0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
1 - MIPI CSI-2 C-PHY
2 - MIPI CSI1
3 - CCP2
4 - MIPI CSI-2 D-PHY
5 - Parallel
6 - Bt.656
- bus-width: number of data lines actively used, valid for the parallel busses.
- data-shift: on the parallel data busses, if bus-width is used to specify the
number of data lines, data-shift can be used to specify which data lines are

1
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
View File

@ -17,6 +17,7 @@ Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.

3
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
View File

@ -6,6 +6,7 @@ Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
"mediatek,mt8173-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
@ -16,7 +17,7 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
Required property for mt2701 and mt2712:
Required property for mt2701, mt2712 and mt7623:
- mediatek,larb-id :the hardware id of this larb.
Example:

36
Documentation/devicetree/bindings/net/dsa/b53.txt
View File

@ -46,6 +46,42 @@ Required properties:
"brcm,bcm6328-switch"
"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
Required properties for BCM585xx/586xx/88312 SoCs:
- reg: a total of 3 register base addresses, the first one must be the
Switch Register Access block base, the second is the port 5/4 mux
configuration register and the third one is the SGMII configuration
and status register base address.
- interrupts: a total of 13 interrupts must be specified, in the following
order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
then the timestamping interrupt and the sleep timer interrupts for ports
5,7,8.
Optional properties for BCM585xx/586xx/88312 SoCs:
- reg-names: a total of 3 names matching the 3 base register address, must
be in the following order:
"srab"
"mux_config"
"sgmii_config"
- interrupt-names: a total of 13 names matching the 13 interrupts specified
must be in the following order:
"link_state_p0"
"link_state_p1"
"link_state_p2"
"link_state_p3"
"link_state_p4"
"link_state_p5"
"link_state_p7"
"link_state_p8"
"phy"
"ts"
"imp_sleep_timer_p5"
"imp_sleep_timer_p7"
"imp_sleep_timer_p8"
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.

4
Documentation/devicetree/bindings/net/marvell,prestera.txt
View File

@ -2,7 +2,7 @@ Marvell Prestera Switch Chip bindings
-------------------------------------
Required properties:
- compatible: one of the following
- compatible: must be "marvell,prestera" and one of the following
"marvell,prestera-98dx3236",
"marvell,prestera-98dx3336",
"marvell,prestera-98dx4251",
@ -21,7 +21,7 @@ switch {
ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
packet-processor@0 {
compatible = "marvell,prestera-98dx3236";
compatible = "marvell,prestera-98dx3236", "marvell,prestera";
reg = <0 0x4000000>;
interrupts = <33>, <34>, <35>;
dfx = <&dfx>;

1
Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
View File

@ -7,6 +7,7 @@ Required properties:
"allwinner,sun8i-a83t-sid"
"allwinner,sun8i-h3-sid"
"allwinner,sun50i-a64-sid"
"allwinner,sun50i-h5-sid"
- reg: Should contain registers location and length

2
Documentation/devicetree/bindings/power/actions,owl-sps.txt
View File

@ -3,11 +3,13 @@ Actions Semi Owl Smart Power System (SPS)
Required properties:
- compatible : "actions,s500-sps" for S500
"actions,s700-sps" for S700
"actions,s900-sps" for S900
- reg : Offset and length of the register set for the device.
- #power-domain-cells : Must be 1.
See macros in:
include/dt-bindings/power/owl-s500-powergate.h for S500
include/dt-bindings/power/owl-s700-powergate.h for S700
include/dt-bindings/power/owl-s900-powergate.h for S900
Example:

2
Documentation/devicetree/bindings/power/renesas,apmu.txt
View File

@ -8,7 +8,9 @@ Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
- "renesas,r8a7743-apmu" (RZ/G1M)
- "renesas,r8a7744-apmu" (RZ/G1N)
- "renesas,r8a7745-apmu" (RZ/G1E)
- "renesas,r8a77470-apmu" (RZ/G1C)
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)

3
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
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@ -8,8 +8,11 @@ and various coprocessors.
Required properties:
- compatible: Must contain exactly one of the following:
- "renesas,r8a7743-sysc" (RZ/G1M)
- "renesas,r8a7744-sysc" (RZ/G1N)
- "renesas,r8a7745-sysc" (RZ/G1E)
- "renesas,r8a77470-sysc" (RZ/G1C)
- "renesas,r8a774a1-sysc" (RZ/G2M)
- "renesas,r8a774c0-sysc" (RZ/G2E)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)

126
Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt 100644
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@ -0,0 +1,126 @@
Qualcomm Technology Inc. ADSP Peripheral Image Loader
This document defines the binding for a component that loads and boots firmware
on the Qualcomm Technology Inc. ADSP Hexagon core.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,sdm845-adsp-pil"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: must specify the base address and size of the qdsp6ss register
- interrupts-extended:
Usage: required
Value type: <prop-encoded-array>
Definition: must list the watchdog, fatal IRQs ready, handover and
stop-ack IRQs
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: List of 8 phandle and clock specifier pairs for the adsp.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: List of clock input name strings sorted in the same
order as the clocks property. Definition must have
"xo", "sway_cbcr", "lpass_aon", "lpass_ahbs_aon_cbcr",
"lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
and "qdsp6ss_core".
- power-domains:
Usage: required
Value type: <phandle>
Definition: reference to cx power domain node.
- resets:
Usage: required
Value type: <phandle>
Definition: reference to the list of 2 reset-controller for the adsp.
- reset-names:
Usage: required
Value type: <stringlist>
Definition: must be "pdc_sync" and "cc_lpass"
- qcom,halt-regs:
Usage: required
Value type: <prop-encoded-array>
Definition: a phandle reference to a syscon representing TCSR followed
by the offset within syscon for lpass halt register.
- memory-region:
Usage: required
Value type: <phandle>
Definition: reference to the reserved-memory for the ADSP
- qcom,smem-states:
Usage: required
Value type: <phandle>
Definition: reference to the smem state for requesting the ADSP to
shut down
- qcom,smem-state-names:
Usage: required
Value type: <stringlist>
Definition: must be "stop"
= SUBNODES
The adsp node may have an subnode named "glink-edge" that describes the
communication edge, channels and devices related to the ADSP.
See ../soc/qcom/qcom,glink.txt for details on how to describe these.
= EXAMPLE
The following example describes the resources needed to boot control the
ADSP, as it is found on SDM845 boards.
remoteproc@17300000 {
compatible = "qcom,sdm845-adsp-pil";
reg = <0x17300000 0x40c>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_LPASS_SWAY_CLK>,
<&lpasscc LPASS_AUDIO_WRAPPER_AON_CLK>,
<&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
<&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
<&lpasscc LPASS_QDSP6SS_XO_CLK>,
<&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
<&lpasscc LPASS_QDSP6SS_CORE_CLK>;
clock-names = "xo", "sway_cbcr", "lpass_aon",
"lpass_ahbs_aon_cbcr",
"lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
"qdsp6ss_sleep", "qdsp6ss_core";
power-domains = <&rpmhpd SDM845_CX>;
resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
<&aoss_reset AOSS_CC_LPASS_RESTART>;
reset-names = "pdc_sync", "cc_lpass";
qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
memory-region = <&pil_adsp_mem>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
};

5
Documentation/devicetree/bindings/remoteproc/qcom,adsp.txt
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@ -10,6 +10,11 @@ on the Qualcomm ADSP Hexagon core.
"qcom,msm8974-adsp-pil"
"qcom,msm8996-adsp-pil"
"qcom,msm8996-slpi-pil"
"qcom,qcs404-adsp-pas"
"qcom,qcs404-cdsp-pas"
"qcom,qcs404-wcss-pas"
"qcom,sdm845-adsp-pas"
"qcom,sdm845-cdsp-pas"
- interrupts-extended:
Usage: required

8
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
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@ -53,13 +53,17 @@ on the Qualcomm Hexagon core.
Definition: reference to the reset-controller for the modem sub-system
reference to the list of 3 reset-controllers for the
wcss sub-system
reference to the list of 2 reset-controllers for the modem
sub-system on SDM845 SoCs
- reset-names:
Usage: required
Value type: <stringlist>
Definition: must be "mss_restart" for the modem sub-system
Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss syb-system
must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
for the wcss sub-system
must be "mss_restart", "pdc_reset" for the modem
sub-system on SDM845 SoCs
- cx-supply:
- mss-supply:

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