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clk: uniphier: Add SCSSI clock gate for each channel 

[ Upstream commit 1ec09a2ec6 ]

SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.

Fixes: ff388ee365 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
5.4-rM2-2.2.x-imx-squashed
Kunihiko Hayashi 2019-12-27 10:42:05 +09:00 committed by Greg Kroah-Hartman
parent 6447bfe829
commit 2417ea1d07
1 changed files with 8 additions and 5 deletions
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13
drivers/clk/uniphier/clk-uniphier-peri.c
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@ -18,8 +18,8 @@
#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
#define UNIPHIER_PERI_CLK_SCSSI(idx) \
UNIPHIER_CLK_GATE("scssi", (idx), "spi", 0x20, 17)
#define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \
UNIPHIER_CLK_GATE("scssi" #ch, (idx), "spi", 0x20, 17 + (ch))
#define UNIPHIER_PERI_CLK_MCSSI(idx) \
UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
@ -35,7 +35,7 @@ const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
UNIPHIER_PERI_CLK_I2C(6, 2),
UNIPHIER_PERI_CLK_I2C(7, 3),
UNIPHIER_PERI_CLK_I2C(8, 4),
UNIPHIER_PERI_CLK_SCSSI(11),
UNIPHIER_PERI_CLK_SCSSI(11, 0),
{ /* sentinel */ }
};
@ -51,7 +51,10 @@ const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
UNIPHIER_PERI_CLK_FI2C(8, 4),
UNIPHIER_PERI_CLK_FI2C(9, 5),
UNIPHIER_PERI_CLK_FI2C(10, 6),
UNIPHIER_PERI_CLK_SCSSI(11),
UNIPHIER_PERI_CLK_MCSSI(12),
UNIPHIER_PERI_CLK_SCSSI(11, 0),
UNIPHIER_PERI_CLK_SCSSI(12, 1),
UNIPHIER_PERI_CLK_SCSSI(13, 2),
UNIPHIER_PERI_CLK_SCSSI(14, 3),
UNIPHIER_PERI_CLK_MCSSI(15),
{ /* sentinel */ }
};