drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode must be applied using LRIs on gen8. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
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/* WaDisableAsyncFlipPerfMode:bdw */
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WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
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/* WaDisablePartialInstShootdown:bdw */
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/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
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WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
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/* WaDisableAsyncFlipPerfMode:chv */
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WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
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/* WaDisablePartialInstShootdown:chv */
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/* WaDisableThreadStallDopClockGating:chv */
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
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* to use MI_WAIT_FOR_EVENT within the CS. It should already be
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* programmed to '1' on all products.
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*
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* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
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* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
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*/
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if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
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if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
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I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
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/* Required for the hardware to program scanline values for waiting */
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