ath9k: add comments for ath9k_hw_configpcipowersave()
This is used for ASPM. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -2632,6 +2632,15 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
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return status;
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}
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/*
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* Helper for ASPM support.
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*
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* Disable PLL when in L0s as well as receiver clock when in L1.
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* This power saving option must be enabled through the SerDes.
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*
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* Programming the SerDes must go through the same 288 bit serial shift
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* register as the other analog registers. Hence the 9 writes.
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*/
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void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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{
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u8 i;
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@ -2639,13 +2648,20 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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if (ah->is_pciexpress != true)
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return;
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/* Do not touch SerDes registers */
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if (ah->config.pcie_powersave_enable == 2)
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return;
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/* Nothing to do on restore for 11N */
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if (restore)
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return;
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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/*
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* AR9280 2.0 or later chips use SerDes values from the
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* initvals.h initialized depending on chipset during
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* ath9k_hw_do_attach()
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*/
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for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
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REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
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INI_RA(&ah->iniPcieSerdes, i, 1));
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@ -2656,10 +2672,12 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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/* RX shut off when elecidle is asserted */
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REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
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REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
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/* Shut off CLKREQ active in L1 */
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if (ah->config.pcie_clock_req)
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REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
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else
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@ -2669,29 +2687,46 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
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/* Load the new settings */
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REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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udelay(1000);
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} else {
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REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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/* RX shut off when elecidle is asserted */
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REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
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REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
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/*
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* Ignore ah->ah_config.pcie_clock_req setting for
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* pre-AR9280 11n
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*/
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REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
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REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
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REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
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/* Load the new settings */
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REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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}
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/* set bit 19 to allow forcing of pcie core into L1 state */
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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/* Several PCIe massages to ensure proper behaviour */
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if (ah->config.pcie_waen) {
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REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
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} else {
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if (AR_SREV_9285(ah))
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REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
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/*
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* On AR9280 chips bit 22 of 0x4004 needs to be set to
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* otherwise card may disappear.
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*/
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else if (AR_SREV_9280(ah))
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REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
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else
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