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ARM: l2c: cns3xxx: remove cache size override

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The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2014-03-19 12:06:27 +00:00
parent a048711c0b
commit 24cb65feab
1 changed files with 1 additions and 1 deletions
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2
arch/arm/mach-cns3xxx/core.c
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@ -290,7 +290,7 @@ void __init cns3xxx_l2x0_init(void)
writel(val, base + L310_DATA_LATENCY_CTRL); writel(val, base + L310_DATA_LATENCY_CTRL);
/* 32 KiB, 8-way, parity disable */ /* 32 KiB, 8-way, parity disable */
l2x0_init(base, 0x00540000, 0xfe000fff); l2x0_init(base, 0x00500000, 0xfe0f0fff);
} }
#endif /* CONFIG_CACHE_L2X0 */ #endif /* CONFIG_CACHE_L2X0 */