ARM: gic: Use cpu pm notifiers to save gic state
When the cpu is powered down in a low power mode, the gic cpu interface may be reset, and when the cpu cluster is powered down, the gic distributor may also be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the gic cpu interface registers, and the CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save and restore the gic distributor registers. Original-author: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>hifive-unleashed-5.1
Colin Cross
Santosh Shilimkar
parent
1fb9026344
commit
254056f3b1
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@ -26,6 +26,7 @@
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include <linux/cpu_pm.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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@ -276,6 +277,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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if (gic_irqs > 1020)
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gic_irqs = 1020;
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gic->gic_irqs = gic_irqs;
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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@ -343,6 +346,189 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
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writel_relaxed(1, base + GIC_CPU_CTRL);
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}
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#ifdef CONFIG_CPU_PM
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/*
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* Saves the GIC distributor registers during suspend or idle. Must be called
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* with interrupts disabled but before powering down the GIC. After calling
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* this function, no interrupts will be delivered by the GIC, and another
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* platform-specific wakeup source must be enabled.
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*/
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static void gic_dist_save(unsigned int gic_nr)
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{
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unsigned int gic_irqs;
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void __iomem *dist_base;
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int i;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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gic_irqs = gic_data[gic_nr].gic_irqs;
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dist_base = gic_data[gic_nr].dist_base;
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if (!dist_base)
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return;
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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gic_data[gic_nr].saved_spi_conf[i] =
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readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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gic_data[gic_nr].saved_spi_target[i] =
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readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
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gic_data[gic_nr].saved_spi_enable[i] =
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readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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}
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/*
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* Restores the GIC distributor registers during resume or when coming out of
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* idle. Must be called before enabling interrupts. If a level interrupt
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* that occured while the GIC was suspended is still present, it will be
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* handled normally, but any edge interrupts that occured will not be seen by
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* the GIC and need to be handled by the platform-specific wakeup source.
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*/
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static void gic_dist_restore(unsigned int gic_nr)
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{
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unsigned int gic_irqs;
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unsigned int i;
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void __iomem *dist_base;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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gic_irqs = gic_data[gic_nr].gic_irqs;
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dist_base = gic_data[gic_nr].dist_base;
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if (!dist_base)
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return;
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writel_relaxed(0, dist_base + GIC_DIST_CTRL);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
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dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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writel_relaxed(0xa0a0a0a0,
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dist_base + GIC_DIST_PRI + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
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dist_base + GIC_DIST_TARGET + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
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writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
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dist_base + GIC_DIST_ENABLE_SET + i * 4);
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writel_relaxed(1, dist_base + GIC_DIST_CTRL);
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}
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static void gic_cpu_save(unsigned int gic_nr)
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{
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int i;
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u32 *ptr;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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dist_base = gic_data[gic_nr].dist_base;
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cpu_base = gic_data[gic_nr].cpu_base;
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if (!dist_base || !cpu_base)
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return;
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ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
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for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
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ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
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for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
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ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
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}
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static void gic_cpu_restore(unsigned int gic_nr)
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{
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int i;
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u32 *ptr;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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dist_base = gic_data[gic_nr].dist_base;
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cpu_base = gic_data[gic_nr].cpu_base;
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if (!dist_base || !cpu_base)
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return;
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ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
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for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
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writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
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ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
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for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
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writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
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writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
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writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
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writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
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}
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static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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{
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int i;
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for (i = 0; i < MAX_GIC_NR; i++) {
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switch (cmd) {
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case CPU_PM_ENTER:
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gic_cpu_save(i);
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break;
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case CPU_PM_ENTER_FAILED:
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case CPU_PM_EXIT:
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gic_cpu_restore(i);
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break;
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case CPU_CLUSTER_PM_ENTER:
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gic_dist_save(i);
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break;
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case CPU_CLUSTER_PM_ENTER_FAILED:
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case CPU_CLUSTER_PM_EXIT:
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gic_dist_restore(i);
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break;
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}
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}
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return NOTIFY_OK;
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}
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static struct notifier_block gic_notifier_block = {
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.notifier_call = gic_notifier,
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};
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static void __init gic_pm_init(struct gic_chip_data *gic)
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{
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gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
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sizeof(u32));
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BUG_ON(!gic->saved_ppi_enable);
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gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
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sizeof(u32));
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BUG_ON(!gic->saved_ppi_conf);
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cpu_pm_register_notifier(&gic_notifier_block);
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}
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#else
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static void __init gic_pm_init(struct gic_chip_data *gic)
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{
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}
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#endif
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void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
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void __iomem *dist_base, void __iomem *cpu_base)
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{
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@ -360,6 +546,7 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
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gic_dist_init(gic, irq_start);
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gic_cpu_init(gic);
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gic_pm_init(gic);
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}
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void __cpuinit gic_secondary_init(unsigned int gic_nr)
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@ -46,6 +46,14 @@ struct gic_chip_data {
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unsigned int irq_offset;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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#ifdef CONFIG_CPU_PM
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u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
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u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
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u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
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u32 __percpu *saved_ppi_enable;
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u32 __percpu *saved_ppi_conf;
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#endif
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unsigned int gic_irqs;
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};
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#endif
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