ARM: CSR: PM: add sleep entry for SiRFprimaII
This patch adds suspend-to-mem support for prima2. It will make prima2 enter DEEPSLEEP mode while accepting PM_SUSPEND_MEM command. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Rongjun Ying
Barry Song
parent
9c2a51faab
commit
2558bd99cb
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@ -6,3 +6,4 @@ obj-y += prima2.o
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obj-y += rtciobrg.o
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obj-$(CONFIG_DEBUG_LL) += lluart.o
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obj-$(CONFIG_CACHE_L2X0) += l2x0.o
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obj-$(CONFIG_SUSPEND) += pm.o sleep.o
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@ -0,0 +1,149 @@
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/*
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* power management entry for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/suspend.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/rtc/sirfsoc_rtciobrg.h>
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#include <asm/suspend.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "pm.h"
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/*
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* suspend asm codes will access these to make DRAM become self-refresh and
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* system sleep
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*/
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u32 sirfsoc_pwrc_base;
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void __iomem *sirfsoc_memc_base;
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static void sirfsoc_set_wakeup_source(void)
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{
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u32 pwr_trigger_en_reg;
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pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
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SIRFSOC_PWRC_TRIGGER_EN);
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#define X_ON_KEY_B (1 << 0)
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sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
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sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
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}
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static void sirfsoc_set_sleep_mode(u32 mode)
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{
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u32 sleep_mode = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
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SIRFSOC_PWRC_PDN_CTRL);
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sleep_mode &= ~(SIRFSOC_SLEEP_MODE_MASK << 1);
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sleep_mode |= mode << 1;
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sirfsoc_rtc_iobrg_writel(sleep_mode, sirfsoc_pwrc_base +
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SIRFSOC_PWRC_PDN_CTRL);
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}
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static int sirfsoc_pre_suspend_power_off(void)
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{
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u32 wakeup_entry = virt_to_phys(cpu_resume);
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sirfsoc_rtc_iobrg_writel(wakeup_entry, sirfsoc_pwrc_base +
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SIRFSOC_PWRC_SCRATCH_PAD1);
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sirfsoc_set_wakeup_source();
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sirfsoc_set_sleep_mode(SIRFSOC_DEEP_SLEEP_MODE);
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return 0;
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}
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static int sirfsoc_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_MEM:
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sirfsoc_pre_suspend_power_off();
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outer_flush_all();
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outer_disable();
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/* go zzz */
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cpu_suspend(0, sirfsoc_finish_suspend);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct platform_suspend_ops sirfsoc_pm_ops = {
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.enter = sirfsoc_pm_enter,
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.valid = suspend_valid_only_mem,
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};
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static int __init sirfsoc_pm_init(void)
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{
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suspend_set_ops(&sirfsoc_pm_ops);
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return 0;
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}
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late_initcall(sirfsoc_pm_init);
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static const struct of_device_id pwrc_ids[] = {
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{ .compatible = "sirf,prima2-pwrc" },
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{}
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};
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static int __init sirfsoc_of_pwrc_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, pwrc_ids);
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if (!np)
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panic("unable to find compatible pwrc node in dtb\n");
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/*
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* pwrc behind rtciobrg is not located in memory space
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* though the property is named reg. reg only means base
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* offset for pwrc. then of_iomap is not suitable here.
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*/
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if (of_property_read_u32(np, "reg", &sirfsoc_pwrc_base))
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panic("unable to find base address of pwrc node in dtb\n");
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of_node_put(np);
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return 0;
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}
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postcore_initcall(sirfsoc_of_pwrc_init);
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static const struct of_device_id memc_ids[] = {
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{ .compatible = "sirf,prima2-memc" },
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{}
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};
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static int __devinit sirfsoc_memc_probe(struct platform_device *op)
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{
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struct device_node *np = op->dev.of_node;
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sirfsoc_memc_base = of_iomap(np, 0);
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if (!sirfsoc_memc_base)
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panic("unable to map memc registers\n");
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return 0;
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}
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static struct platform_driver sirfsoc_memc_driver = {
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.probe = sirfsoc_memc_probe,
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.driver = {
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.name = "sirfsoc-memc",
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.owner = THIS_MODULE,
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.of_match_table = memc_ids,
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},
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};
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static int __init sirfsoc_memc_init(void)
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{
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return platform_driver_register(&sirfsoc_memc_driver);
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}
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postcore_initcall(sirfsoc_memc_init);
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@ -0,0 +1,29 @@
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/*
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* arch/arm/mach-prima2/pm.h
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#ifndef _MACH_PRIMA2_PM_H_
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#define _MACH_PRIMA2_PM_H_
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#define SIRFSOC_PWR_SLEEPFORCE 0x01
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#define SIRFSOC_SLEEP_MODE_MASK 0x3
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#define SIRFSOC_DEEP_SLEEP_MODE 0x1
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#define SIRFSOC_PWRC_PDN_CTRL 0x0
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#define SIRFSOC_PWRC_PON_OFF 0x4
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#define SIRFSOC_PWRC_TRIGGER_EN 0x8
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#define SIRFSOC_PWRC_PIN_STATUS 0x14
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#define SIRFSOC_PWRC_SCRATCH_PAD1 0x18
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#define SIRFSOC_PWRC_SCRATCH_PAD2 0x1C
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#ifndef __ASSEMBLY__
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extern int sirfsoc_finish_suspend(unsigned long);
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#endif
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#endif
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@ -0,0 +1,64 @@
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/*
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* sleep mode for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/assembler.h>
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#include "pm.h"
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#define DENALI_CTL_22_OFF 0x58
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#define DENALI_CTL_112_OFF 0x1c0
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.text
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ENTRY(sirfsoc_finish_suspend)
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@ r5: mem controller
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ldr r0, =sirfsoc_memc_base
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ldr r5, [r0]
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@ r6: pwrc base offset
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ldr r0, =sirfsoc_pwrc_base
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ldr r6, [r0]
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@ r7: rtc iobrg controller
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ldr r0, =sirfsoc_rtciobrg_base
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ldr r7, [r0]
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@ Read the power control register and set the
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@ sleep force bit.
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add r0, r6, #SIRFSOC_PWRC_PDN_CTRL
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bl __sirfsoc_rtc_iobrg_readl
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orr r0,r0,#SIRFSOC_PWR_SLEEPFORCE
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add r1, r6, #SIRFSOC_PWRC_PDN_CTRL
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bl sirfsoc_rtc_iobrg_pre_writel
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mov r1, #0x1
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@ read the MEM ctl register and set the self
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@ refresh bit
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ldr r2, [r5, #DENALI_CTL_22_OFF]
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orr r2, r2, #0x1
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@ Following code has to run from cache since
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@ the RAM is going to self refresh mode
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.align 5
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str r2, [r5, #DENALI_CTL_22_OFF]
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1:
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ldr r4, [r5, #DENALI_CTL_112_OFF]
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tst r4, #0x1
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bne 1b
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@ write SLEEPFORCE through rtc iobridge
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str r1, [r7]
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@ wait rtc io bridge sync
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1:
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ldr r3, [r7]
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tst r3, #0x01
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bne 1b
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b .
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