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OMAP4: clocks: Update the clock tree with 4460 clock nodes

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Add the new clock nodes (bandgap_ts_fclk, div_ts_ck) for omap4460.
Handle these nodes using the clock flags (CK_*).

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Rajendra Nayak 2011-07-02 08:00:24 +05:30 committed by Tony Lindgren
parent 6b54b49912
commit 257d643d7d
3 changed files with 42 additions and 0 deletions
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39
arch/arm/mach-omap2/clock44xx_data.c
View file

@ -1486,6 +1486,40 @@ static struct clk dss_dss_clk = {
.recalc = &followparent_recalc,
};
static const struct clksel_rate div3_8to32_rates[] = {
{ .div = 8, .val = 0, .flags = RATE_IN_44XX },
{ .div = 16, .val = 1, .flags = RATE_IN_44XX },
{ .div = 32, .val = 2, .flags = RATE_IN_44XX },
{ .div = 0 },
};
static const struct clksel div_ts_div[] = {
{ .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
{ .parent = NULL },
};
static struct clk div_ts_ck = {
.name = "div_ts_ck",
.parent = &l4_wkup_clk_mux_ck,
.clksel = div_ts_div,
.clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk bandgap_ts_fclk = {
.name = "bandgap_ts_fclk",
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
.enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
.clkdm_name = "l4_wkup_clkdm",
.parent = &div_ts_ck,
.recalc = &followparent_recalc,
};
static struct clk dss_48mhz_clk = {
.name = "dss_48mhz_clk",
.ops = &clkops_omap2_dflt,
@ -3110,7 +3144,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
CLK(NULL, "aess_fck", &aess_fck, CK_443X),
CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
@ -3293,6 +3329,9 @@ int __init omap4xxx_clk_init(void)
if (cpu_is_omap44xx()) {
cpu_mask = RATE_IN_4430;
cpu_clkflg = CK_443X;
} else if (cpu_is_omap446x()) {
cpu_mask = RATE_IN_4460;
cpu_clkflg = CK_446X;
}
clk_init(&omap2_clk_functions);

1
arch/arm/plat-omap/include/plat/clkdev_omap.h
View file

@ -39,6 +39,7 @@ struct omap_clk {
#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
#define CK_446X (1 << 13)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)

2
arch/arm/plat-omap/include/plat/clock.h
View file

@ -58,10 +58,12 @@ struct clkops {
#define RATE_IN_36XX (1 << 4)
#define RATE_IN_4430 (1 << 5)
#define RATE_IN_TI816X (1 << 6)
#define RATE_IN_4460 (1 << 7)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)