staging: dgnc: neo_uart_struct: adds marker and changes vars' types for sparse
This patch fixes these warnings found in the neo.c file: warning: incorrect type in argument 1 (different address spaces) expected void const volatile [noderef] <asn:2>*addr got unsigned char volatile *<noident> warning: incorrect type in argument 2 (different address spaces) expected void volatile [noderef] <asn:2>*addr got unsigned char volatile *<noident> The variables passed to readb and writeb need to be of type u8 with a __iomem marker. These warnings were popping up everytime the readb and writeb functions were called with a neo_uart_struct variable. The change made to the driver.h file adds the marker to the neo_uart_struct and the changes in neo.h changes the variables' types. Signed-off-by: Lidza Louina <lidza.louina@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -480,7 +480,7 @@ struct channel_t {
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uchar ch_mostat; /* FEP output modem status */
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uchar ch_mostat; /* FEP output modem status */
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uchar ch_mistat; /* FEP input modem status */
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uchar ch_mistat; /* FEP input modem status */
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struct neo_uart_struct *ch_neo_uart; /* Pointer to the "mapped" UART struct */
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struct neo_uart_struct __iomem *ch_neo_uart; /* Pointer to the "mapped" UART struct */
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struct cls_uart_struct __iomem *ch_cls_uart; /* Pointer to the "mapped" UART struct */
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struct cls_uart_struct __iomem *ch_cls_uart; /* Pointer to the "mapped" UART struct */
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uchar ch_cached_lsr; /* Cached value of the LSR register */
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uchar ch_cached_lsr; /* Cached value of the LSR register */
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@ -36,27 +36,27 @@
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************************************************************************/
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************************************************************************/
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struct neo_uart_struct {
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struct neo_uart_struct {
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volatile uchar txrx; /* WR RHR/THR - Holding Reg */
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u8 txrx; /* WR RHR/THR - Holding Reg */
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volatile uchar ier; /* WR IER - Interrupt Enable Reg */
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u8 ier; /* WR IER - Interrupt Enable Reg */
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volatile uchar isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
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u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
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volatile uchar lcr; /* WR LCR - Line Control Reg */
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u8 lcr; /* WR LCR - Line Control Reg */
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volatile uchar mcr; /* WR MCR - Modem Control Reg */
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u8 mcr; /* WR MCR - Modem Control Reg */
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volatile uchar lsr; /* WR LSR - Line Status Reg */
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u8 lsr; /* WR LSR - Line Status Reg */
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volatile uchar msr; /* WR MSR - Modem Status Reg */
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u8 msr; /* WR MSR - Modem Status Reg */
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volatile uchar spr; /* WR SPR - Scratch Pad Reg */
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u8 spr; /* WR SPR - Scratch Pad Reg */
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volatile uchar fctr; /* WR FCTR - Feature Control Reg */
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u8 fctr; /* WR FCTR - Feature Control Reg */
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volatile uchar efr; /* WR EFR - Enhanced Function Reg */
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u8 efr; /* WR EFR - Enhanced Function Reg */
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volatile uchar tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
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u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
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volatile uchar rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */
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u8 rfifo; /* WR RXCNT/RXTRG - Recieve FIFO Reg */
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volatile uchar xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
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u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
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volatile uchar xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
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u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
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volatile uchar xonchar1; /* WR XON 1 - Xon Character 1 Reg */
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u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
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volatile uchar xonchar2; /* WR XON 2 - XOn Character 2 Reg */
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u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
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volatile uchar reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
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u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
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volatile uchar txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
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u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
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volatile uchar reserved2[0x37f - 0x340]; /* U Reserved by Exar */
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u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
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volatile uchar rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
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u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
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};
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};
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/* Where to read the extended interrupt register (32bits instead of 8bits) */
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/* Where to read the extended interrupt register (32bits instead of 8bits) */
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