drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
For BXT, description of polarities of PORT_PLL_REF_SEL has been reversed for newer Gen9LP steppings according to the recent update in Bspec. This bit now should be set for "Non-SSC" mode for all Gen9LP starting from B0 stepping. v2: Only B0 and newer stepping should be affected by this change. Signed-off-by: Dongwon Kim <dongwon.kim@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94866 Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458176773-26925-1-git-send-email-dongwon.kim@intel.com
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@ -1296,7 +1296,15 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
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temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
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temp &= ~PORT_PLL_REF_SEL;
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/*
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* Definition of each bit polarity has been changed
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* after A1 stepping
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*/
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if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
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temp &= ~PORT_PLL_REF_SEL;
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else
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temp |= PORT_PLL_REF_SEL;
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/* Non-SSC reference */
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I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
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