redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

ARM: 8602/1: factor out CSSELR/CCSIDR operations that use cp15 directly 

Currently we use raw cp15 operations to access the cache setup data.

This patch abstracts the CSSELR and CCSIDR accessors out to a header so
that the implementation for them can be switched out as we do with other
cpu/cachetype operations.

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
hifive-unleashed-5.1
Jonathan Austin 2016-08-30 17:24:34 +01:00 committed by Russell King
parent 5a0e069114
commit 26150aa96d
2 changed files with 26 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/include/asm/cachetype.h
View File

@ -56,4 +56,28 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
(~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
}
#define CSSELR_ICACHE 1
#define CSSELR_DCACHE 0
#define CSSELR_L1 (0 << 1)
#define CSSELR_L2 (1 << 1)
#define CSSELR_L3 (2 << 1)
#define CSSELR_L4 (3 << 1)
#define CSSELR_L5 (4 << 1)
#define CSSELR_L6 (5 << 1)
#define CSSELR_L7 (6 << 1)
static inline void set_csselr(unsigned int cache_selector)
{
asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
}
static inline unsigned int read_ccsidr(void)
{
unsigned int val;
asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
return val;
}
#endif

7
arch/arm/kernel/setup.c
View File

@ -290,12 +290,9 @@ static int cpu_has_aliasing_icache(unsigned int arch)
/* arch specifies the register format */
switch (arch) {
case CPU_ARCH_ARMv7:
asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
: /* No output operands */
: "r" (1));
set_csselr(CSSELR_ICACHE | CSSELR_L1);
isb();
asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
: "=r" (id_reg));
id_reg = read_ccsidr();
line_size = 4 << ((id_reg & 0x7) + 2);
num_sets = ((id_reg >> 13) & 0x7fff) + 1;
aliasing_icache = (line_size * num_sets) > PAGE_SIZE;