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Merge branch 'fixes-non-critical-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

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* 'fixes-non-critical-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP3+: PM: VP: fix integer truncation error
  ARM: OMAP2+: PM: fix wakeupgen warning when hotplug disabled
  ARM: OMAP2+: PM: fix section mismatch with omap2_init_processor_devices()
  ARM: OMAP2: Fix section warning for n8x0 when CONFIG_MMC_OMAP is not set
  ARM: OMAP2+: Fix omap24xx_io_desc warning if SoC subtypes are not selected
  ARM: OMAP1: Fix section mismatch for omap1_init_early()
  ARM: OMAP1: Fix typo in lcd_dma.c
  ARM: OMAP: mailbox: trivial whitespace fix
  ARM: OMAP: Remove definition cpu_is_omap4430()
  ARM: OMAP2+: included some headers twice
  ARM: OMAP: clock.c: included linux/debugfs.h twice
  ARM: OMAP: don't build hwspinlock in vain
  ARM: OMAP2+: ads7846_init: put gpio_pendown into pdata if it's provided
  ARM: omap: pandora: fix usbhs platform data
  ARM: OMAP: sram: Add am33xx SRAM support (minimal)
  ARM: OMAP2+: id: Add am33xx SoC type detection
  ARM: OMAP2+: GPMC: Export gpmc_enable_hwecc and gpmc_calculate_ecc
  ARM: OMAP: dmtimer: fix missing content/correction in low-power mode support
This commit is contained in:
Olof Johansson 2012-03-07 15:02:47 -08:00
parent 412fe6b3a1 3223d007a3
commit 269f6a93f6
21 changed files with 90 additions and 56 deletions
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2
arch/arm/mach-omap1/io.c
View file

@ -118,7 +118,7 @@ void __init omap16xx_map_io(void)
/*
* Common low-level hardware init for omap1.
*/
void omap1_init_early(void)
void __init omap1_init_early(void)
{
omap_check_revision();

2
arch/arm/mach-omap1/lcd_dma.c
View file

@ -117,7 +117,7 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (cpu_is_omap15xx()) {
printk(KERN_ERR "DMA virtual resulotion is not supported "
printk(KERN_ERR "DMA virtual resolution is not supported "
"in 1510 mode\n");
BUG();
}

4
arch/arm/mach-omap2/Makefile
View file

@ -265,6 +265,8 @@ obj-y += $(smc91x-m) $(smc91x-y)
smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
obj-y += $(smsc911x-m) $(smsc911x-y)
obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
obj-y += hwspinlock.o
endif
obj-y += common-board-devices.o twl-common.o

1
arch/arm/mach-omap2/board-ldp.c
View file

@ -27,7 +27,6 @@
#include <linux/io.h>
#include <linux/smsc911x.h>
#include <linux/mmc/host.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>

8
arch/arm/mach-omap2/board-n8x0.c
View file

@ -36,10 +36,6 @@
#include "mux.h"
static int slot1_cover_open;
static int slot2_cover_open;
static struct device *mmc_device;
#define TUSB6010_ASYNC_CS 1
#define TUSB6010_SYNC_CS 4
#define TUSB6010_GPIO_INT 58
@ -211,6 +207,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
#define N810_EMMC_VSD_GPIO 23
#define N810_EMMC_VIO_GPIO 9
static int slot1_cover_open;
static int slot2_cover_open;
static struct device *mmc_device;
static int n8x0_mmc_switch_slot(struct device *dev, int slot)
{
#ifdef CONFIG_MMC_DEBUG

10
arch/arm/mach-omap2/board-omap3pandora.c
View file

@ -345,7 +345,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
};
static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
};
/* ads7846 on SPI and 2 nub controllers on I2C */
@ -563,13 +563,13 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
.phy_reset = true,
.reset_gpio_port[0] = 16,
.reset_gpio_port[1] = -EINVAL,
.reset_gpio_port[0] = -EINVAL,
.reset_gpio_port[1] = 16,
.reset_gpio_port[2] = -EINVAL
};

8
arch/arm/mach-omap2/common-board-devices.c
View file

@ -76,13 +76,15 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
gpio_set_debounce(gpio_pendown, gpio_debounce);
}
ads7846_config.gpio_pendown = gpio_pendown;
spi_bi->bus_num = bus_num;
spi_bi->irq = OMAP_GPIO_IRQ(gpio_pendown);
if (board_pdata)
if (board_pdata) {
board_pdata->gpio_pendown = gpio_pendown;
spi_bi->platform_data = board_pdata;
} else {
ads7846_config.gpio_pendown = gpio_pendown;
}
spi_register_board_info(&ads7846_spi_board_info, 1);
}

5
arch/arm/mach-omap2/control.h
View file

@ -338,6 +338,11 @@
#define AM35XX_HECC_SW_RST BIT(3)
#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
/*
* CONTROL AM33XX STATUS register
*/
#define AM33XX_CONTROL_STATUS 0x040
/*
* CONTROL OMAP STATUS register to identify OMAP3 features
*/

2
arch/arm/mach-omap2/gpmc.c
View file

@ -888,6 +888,7 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
gpmc_write_reg(GPMC_ECC_CONFIG, val);
return 0;
}
EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
/**
* gpmc_calculate_ecc - generate non-inverted ecc bytes
@ -918,3 +919,4 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
gpmc_ecc_used = -EINVAL;
return 0;
}
EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);

2
arch/arm/mach-omap2/id.c
View file

@ -44,6 +44,8 @@ int omap_type(void)
if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
} else if (cpu_is_am33xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
} else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {

3
arch/arm/mach-omap2/io.c
View file

@ -43,14 +43,13 @@
#include "clockdomain.h"
#include <plat/omap_hwmod.h>
#include <plat/multi.h>
#include "common.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
#ifdef CONFIG_ARCH_OMAP2
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
static struct map_desc omap24xx_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,

53
arch/arm/mach-omap2/omap-wakeupgen.c
View file

@ -43,7 +43,6 @@
static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
static DEFINE_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[NR_IRQS];
@ -67,14 +66,6 @@ static inline void sar_writel(u32 val, u32 offset, u8 idx)
__raw_writel(val, sar_base + offset + (idx * 4));
}
static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(reg, i, cpu);
}
static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
{
unsigned int spi_irq;
@ -130,22 +121,6 @@ static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
wakeupgen_writel(val, i, cpu);
}
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
/*
* Architecture specific Mask extension
*/
@ -170,6 +145,33 @@ static void wakeupgen_unmask(struct irq_data *d)
spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
static void _wakeupgen_save_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}
static void _wakeupgen_restore_masks(unsigned int cpu)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}
static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
u8 i;
for (i = 0; i < NR_REG_BANKS; i++)
wakeupgen_writel(reg, i, cpu);
}
/*
* Mask or unmask all interrupts on given CPU.
* 0 = Mask all interrupts on the 'cpu'
@ -191,6 +193,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
}
spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#endif
#ifdef CONFIG_CPU_PM
/*

1
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file

@ -28,7 +28,6 @@
#include <plat/mcspi.h>
#include <plat/mcbsp.h>
#include <plat/mmc.h>
#include <plat/i2c.h>
#include <plat/dmtimer.h>
#include <plat/common.h>

2
arch/arm/mach-omap2/pm.c
View file

@ -49,7 +49,7 @@ static int __init _init_omap_device(char *name)
/*
* Build omap_devices for processors and bus.
*/
static void omap2_init_processor_devices(void)
static void __init omap2_init_processor_devices(void)
{
_init_omap_device("mpu");
if (omap3_has_iva())

4
arch/arm/mach-omap2/vp.c
View file

@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
vddmin = voltdm->pmic->vp_vddmin;
vddmax = voltdm->pmic->vp_vddmax;
waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
sys_clk_rate) / 1000;
waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
1000 * voltdm->pmic->slew_rate);
vstepmin = voltdm->pmic->vp_vstepmin;
vstepmax = voltdm->pmic->vp_vstepmax;

1
arch/arm/plat-omap/clock.c
View file

@ -20,7 +20,6 @@
#include <linux/clk.h>
#include <linux/mutex.h>
#include <linux/cpufreq.h>
#include <linux/debugfs.h>
#include <linux/io.h>
#include <plat/clock.h>

19
arch/arm/plat-omap/dmtimer.c
View file

@ -80,9 +80,9 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
static void omap_timer_restore_context(struct omap_dm_timer *timer)
{
omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
timer->context.tiocp_cfg);
if (timer->revision > 1)
__raw_writel(timer->context.tiocp_cfg,
timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
if (timer->revision == 1)
__raw_writel(timer->context.tistat, timer->sys_stat);
__raw_writel(timer->context.tisr, timer->irq_stat);
@ -357,6 +357,19 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
__omap_dm_timer_stop(timer, timer->posted, rate);
if (timer->loses_context && timer->get_context_loss_count)
timer->ctx_loss_count =
timer->get_context_loss_count(&timer->pdev->dev);
/*
* Since the register values are computed and written within
* __omap_dm_timer_stop, we need to use read to retrieve the
* context.
*/
timer->context.tclr =
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
timer->context.tisr = __raw_readl(timer->irq_stat);
omap_dm_timer_disable(timer);
return 0;
}
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);

2
arch/arm/plat-omap/include/plat/cpu.h
View file

@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
* cpu_is_omap2423(): True for OMAP2423
* cpu_is_omap2430(): True for OMAP2430
* cpu_is_omap3430(): True for OMAP3430
* cpu_is_omap4430(): True for OMAP4430
* cpu_is_omap3505(): True for OMAP3505
* cpu_is_omap3517(): True for OMAP3517
*/
@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
#define cpu_is_omap3505() 0
#define cpu_is_omap3517() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap4430() 0
#define cpu_is_omap3630() 0
/*

1
arch/arm/plat-omap/include/plat/sram.h
View file

@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
#else
#define OMAP4_SRAM_PA 0x40300000
#endif
#define AM33XX_SRAM_PA 0x40300000
#endif

2
arch/arm/plat-omap/mailbox.c
View file

@ -307,7 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
if (!--mbox->use_count) {
free_irq(mbox->irq, mbox);
tasklet_kill(&mbox->txq->tasklet);
flush_work_sync(&mbox->rxq->work);
flush_work_sync(&mbox->rxq->work);
mbox_queue_free(mbox->txq);
mbox_queue_free(mbox->rxq);
}

14
arch/arm/plat-omap/sram.c
View file

@ -86,7 +86,7 @@ static int is_sram_locked(void)
__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
@ -124,7 +124,10 @@ static void __init omap_detect_sram(void)
omap_sram_size = 0x800; /* 2K */
}
} else {
if (cpu_is_omap34xx()) {
if (cpu_is_am33xx()) {
omap_sram_start = AM33XX_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap34xx()) {
omap_sram_start = OMAP3_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap44xx()) {
@ -368,6 +371,11 @@ static inline int omap34xx_sram_init(void)
return 0;
}
static inline int am33xx_sram_init(void)
{
return 0;
}
int __init omap_sram_init(void)
{
omap_detect_sram();
@ -379,6 +387,8 @@ int __init omap_sram_init(void)
omap242x_sram_init();
else if (cpu_is_omap2430())
omap243x_sram_init();
else if (cpu_is_am33xx())
am33xx_sram_init();
else if (cpu_is_omap34xx())
omap34xx_sram_init();