cpufreq: exynos5250: Set APLL rate using CCF API
Use common clock framework (CCF) APIs to set the clock rates instead of direct register manipulation. This now updates the sysfs entry (cpuinfo_cur_freq) correctly which did not reflect the correct value until now. While at it clean up the PLL s-div parameter setting as it is handled by the PLL driver. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -102,12 +102,12 @@ static void set_clkdiv(unsigned int div_index)
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cpu_relax();
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cpu_relax();
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}
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}
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static void set_apll(unsigned int new_index,
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static void set_apll(unsigned int index)
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unsigned int old_index)
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{
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{
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unsigned int tmp, pdiv;
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unsigned int tmp;
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unsigned int freq = apll_freq_5250[index].freq;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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clk_set_parent(moutcore, mout_mpll);
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do {
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do {
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@ -116,24 +116,9 @@ static void set_apll(unsigned int new_index,
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tmp &= 0x7;
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tmp &= 0x7;
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} while (tmp != 0x2);
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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clk_set_rate(mout_apll, freq * 1000);
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pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f);
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__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
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/* MUX_CORE_SEL = APLL */
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= apll_freq_5250[new_index].mps;
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__raw_writel(tmp, EXYNOS5_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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} while (!(tmp & (0x1 << 29)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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clk_set_parent(moutcore, mout_apll);
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do {
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do {
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@ -141,55 +126,17 @@ static void set_apll(unsigned int new_index,
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tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
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tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
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tmp &= (0x7 << 16);
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tmp &= (0x7 << 16);
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} while (tmp != (0x1 << 16));
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} while (tmp != (0x1 << 16));
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}
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static bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
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{
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unsigned int old_pm = apll_freq_5250[old_index].mps >> 8;
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unsigned int new_pm = apll_freq_5250[new_index].mps >> 8;
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return (old_pm == new_pm) ? 0 : 1;
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}
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}
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static void exynos5250_set_frequency(unsigned int old_index,
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static void exynos5250_set_frequency(unsigned int old_index,
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unsigned int new_index)
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unsigned int new_index)
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{
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{
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unsigned int tmp;
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if (old_index > new_index) {
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if (old_index > new_index) {
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if (!exynos5250_pms_change(old_index, new_index)) {
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set_clkdiv(new_index);
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/* 1. Change the system clock divider values */
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set_apll(new_index);
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set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= apll_freq_5250[new_index].mps & 0x7;
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__raw_writel(tmp, EXYNOS5_APLL_CON0);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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set_apll(new_index, old_index);
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}
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} else if (old_index < new_index) {
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} else if (old_index < new_index) {
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if (!exynos5250_pms_change(old_index, new_index)) {
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set_apll(new_index);
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/* 1. Change just s value in apll m,p,s value */
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set_clkdiv(new_index);
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= apll_freq_5250[new_index].mps & 0x7;
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__raw_writel(tmp, EXYNOS5_APLL_CON0);
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/* 2. Change the system clock divider values */
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set_clkdiv(new_index);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the apll m,p,s value */
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set_apll(new_index, old_index);
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/* 2. Change the system clock divider values */
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set_clkdiv(new_index);
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}
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}
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}
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}
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}
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@ -222,7 +169,6 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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info->volt_table = exynos5250_volt_table;
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info->volt_table = exynos5250_volt_table;
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info->freq_table = exynos5250_freq_table;
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info->freq_table = exynos5250_freq_table;
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info->set_freq = exynos5250_set_frequency;
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info->set_freq = exynos5250_set_frequency;
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info->need_apll_change = exynos5250_pms_change;
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return 0;
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return 0;
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