x86, amd: Cleanup init_amd
Distribute family-specific code to corresponding functions. Also, * move the direct mapping splitting around the TSEG SMM area to bsp_init_amd(). * kill ancient comment about what we should do for K5. * merge amd_k7_smp_check() into its only caller init_amd_k7 and drop cpu_has_mp macro. Signed-off-by: Borislav Petkov <bp@suse.de> Link: http://lkml.kernel.org/r/1403609105-8332-3-git-send-email-bp@alien8.de Signed-off-by: H. Peter Anvin <hpa@zytor.com>hifive-unleashed-5.1
Borislav Petkov
H. Peter Anvin
parent
80a208bd39
commit
26bfa5f894
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@ -8,6 +8,7 @@
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#include <asm/processor.h>
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#include <asm/apic.h>
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#include <asm/cpu.h>
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#include <asm/smp.h>
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#include <asm/pci-direct.h>
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#ifdef CONFIG_X86_64
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@ -50,7 +51,6 @@ static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
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return wrmsr_safe_regs(gprs);
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}
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#ifdef CONFIG_X86_32
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/*
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* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
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* misexecution of code under Linux. Owners of such processors should
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@ -70,6 +70,7 @@ __asm__(".globl vide\n\t.align 4\nvide: ret");
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static void init_amd_k5(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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@ -83,11 +84,12 @@ static void init_amd_k5(struct cpuinfo_x86 *c)
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if (inl(CBAR) & CBAR_ENB)
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outl(0 | CBAR_KEY, CBAR);
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}
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#endif
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}
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static void init_amd_k6(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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u32 l, h;
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int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
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@ -176,53 +178,12 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
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/* placeholder for any needed mods */
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return;
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}
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}
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static void amd_k7_smp_check(struct cpuinfo_x86 *c)
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{
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/* calling is from identify_secondary_cpu() ? */
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if (!c->cpu_index)
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return;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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/* Athlon 660/661 is valid. */
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if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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(c->x86_mask == 1)))
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return;
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/* Duron 670 is valid */
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if ((c->x86_model == 7) && (c->x86_mask == 0))
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return;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability
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* bit. It's worth noting that the A5 stepping (662) of some
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* Athlon XP's have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has_mp)
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return;
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/* If we get here, not a certified SMP capable AMD system. */
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/*
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* Don't taint if we are running SMP kernel on a single non-MP
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* approved Athlon
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*/
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WARN_ONCE(1, "WARNING: This combination of AMD"
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" processors is not suitable for SMP.\n");
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add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
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#endif
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}
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static void init_amd_k7(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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u32 l, h;
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/*
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@ -255,9 +216,47 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_K7);
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amd_k7_smp_check(c);
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}
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/* calling is from identify_secondary_cpu() ? */
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if (!c->cpu_index)
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return;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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/* Athlon 660/661 is valid. */
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if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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(c->x86_mask == 1)))
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return;
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/* Duron 670 is valid */
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if ((c->x86_model == 7) && (c->x86_mask == 0))
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return;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability
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* bit. It's worth noting that the A5 stepping (662) of some
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* Athlon XP's have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has(c, X86_FEATURE_MP))
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return;
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/* If we get here, not a certified SMP capable AMD system. */
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/*
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* Don't taint if we are running SMP kernel on a single non-MP
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* approved Athlon
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*/
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WARN_ONCE(1, "WARNING: This combination of AMD"
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" processors is not suitable for SMP.\n");
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add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
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#endif
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}
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#ifdef CONFIG_NUMA
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/*
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@ -446,6 +445,26 @@ static void early_init_amd_mc(struct cpuinfo_x86 *c)
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static void bsp_init_amd(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_64
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if (c->x86 >= 0xf) {
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unsigned long long tseg;
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/*
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* Split up direct mapping around the TSEG SMM area.
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* Don't do it for gbpages because there seems very little
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* benefit in doing so.
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*/
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if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
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unsigned long pfn = tseg >> PAGE_SHIFT;
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printk(KERN_DEBUG "tseg: %010llx\n", tseg);
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if (pfn_range_is_mapped(pfn, pfn + 1))
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set_memory_4k((unsigned long)__va(tseg), 1);
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}
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}
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#endif
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if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
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if (c->x86 > 0x10 ||
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@ -515,10 +534,100 @@ static const int amd_erratum_383[];
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static const int amd_erratum_400[];
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static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
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static void init_amd_k8(struct cpuinfo_x86 *c)
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{
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u32 level;
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u64 value;
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/* On C+ stepping K8 rep microcode works well for copy/memset */
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level = cpuid_eax(1);
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if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/*
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* Some BIOSes incorrectly force this feature, but only K8 revision D
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* (model = 0x14) and later actually support it.
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* (AMD Erratum #110, docId: 25759).
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*/
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if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
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clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
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if (!rdmsrl_amd_safe(0xc001100d, &value)) {
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value &= ~BIT_64(32);
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wrmsrl_amd_safe(0xc001100d, value);
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}
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}
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if (!c->x86_model_id[0])
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strcpy(c->x86_model_id, "Hammer");
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}
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static void init_amd_gh(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_64
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/* do this for boot cpu */
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if (c == &boot_cpu_data)
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check_enable_amd_mmconf_dmi();
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fam10h_check_enable_mmcfg();
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#endif
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/*
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* Disable GART TLB Walk Errors on Fam10h. We do this here because this
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* is always needed when GART is enabled, even in a kernel which has no
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* MCE support built in. BIOS should disable GartTlbWlk Errors already.
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* If it doesn't, we do it here as suggested by the BKDG.
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*
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* Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
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*/
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msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
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/*
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* On family 10h BIOS may not have properly enabled WC+ support, causing
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* it to be converted to CD memtype. This may result in performance
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* degradation for certain nested-paging guests. Prevent this conversion
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* by clearing bit 24 in MSR_AMD64_BU_CFG2.
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*
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* NOTE: we want to use the _safe accessors so as not to #GP kvm
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* guests on older kvm hosts.
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*/
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msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
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if (cpu_has_amd_erratum(c, amd_erratum_383))
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set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
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}
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static void init_amd_bd(struct cpuinfo_x86 *c)
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{
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u64 value;
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/* re-enable TopologyExtensions if switched off by BIOS */
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if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
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!cpu_has(c, X86_FEATURE_TOPOEXT)) {
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if (msr_set_bit(0xc0011005, 54) > 0) {
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rdmsrl(0xc0011005, value);
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if (value & BIT_64(54)) {
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set_cpu_cap(c, X86_FEATURE_TOPOEXT);
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pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
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}
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}
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}
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/*
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* The way access filter has a performance penalty on some workloads.
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* Disable it on the affected CPUs.
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*/
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if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
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if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
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value |= 0x1E;
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wrmsrl_safe(0xc0011021, value);
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}
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}
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}
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static void init_amd(struct cpuinfo_x86 *c)
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{
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u32 dummy;
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unsigned long long value;
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#ifdef CONFIG_SMP
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/*
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@ -540,100 +649,29 @@ static void init_amd(struct cpuinfo_x86 *c)
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*/
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clear_cpu_cap(c, 0*32+31);
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#ifdef CONFIG_X86_64
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/* On C+ stepping K8 rep microcode works well for copy/memset */
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if (c->x86 == 0xf) {
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u32 level;
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level = cpuid_eax(1);
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if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/*
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* Some BIOSes incorrectly force this feature, but only K8
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* revision D (model = 0x14) and later actually support it.
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* (AMD Erratum #110, docId: 25759).
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*/
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if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
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clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
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if (!rdmsrl_amd_safe(0xc001100d, &value)) {
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value &= ~(1ULL << 32);
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wrmsrl_amd_safe(0xc001100d, value);
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}
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}
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}
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if (c->x86 >= 0x10)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/* get apicid instead of initial apic id from cpuid */
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c->apicid = hard_smp_processor_id();
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#else
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/*
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* FIXME: We should handle the K5 here. Set up the write
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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* no bus pipeline)
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*/
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switch (c->x86) {
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case 4:
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init_amd_k5(c);
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break;
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case 5:
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init_amd_k6(c);
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break;
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case 6: /* An Athlon/Duron */
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init_amd_k7(c);
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break;
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}
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/* K6s reports MCEs but don't actually have all the MSRs */
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if (c->x86 < 6)
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clear_cpu_cap(c, X86_FEATURE_MCE);
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#endif
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switch (c->x86) {
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case 4: init_amd_k5(c); break;
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case 5: init_amd_k6(c); break;
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case 6: init_amd_k7(c); break;
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case 0xf: init_amd_k8(c); break;
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case 0x10: init_amd_gh(c); break;
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case 0x15: init_amd_bd(c); break;
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}
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/* Enable workaround for FXSAVE leak */
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if (c->x86 >= 6)
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set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
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if (!c->x86_model_id[0]) {
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switch (c->x86) {
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case 0xf:
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/* Should distinguish Models here, but this is only
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a fallback anyways. */
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strcpy(c->x86_model_id, "Hammer");
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break;
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}
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}
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/* re-enable TopologyExtensions if switched off by BIOS */
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if ((c->x86 == 0x15) &&
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(c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
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!cpu_has(c, X86_FEATURE_TOPOEXT)) {
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if (msr_set_bit(0xc0011005, 54) > 0) {
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rdmsrl(0xc0011005, value);
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if (value & BIT_64(54)) {
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set_cpu_cap(c, X86_FEATURE_TOPOEXT);
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pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
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}
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}
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}
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/*
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* The way access filter has a performance penalty on some workloads.
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* Disable it on the affected CPUs.
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*/
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if ((c->x86 == 0x15) &&
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(c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
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if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) {
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value |= 0x1E;
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wrmsrl_safe(0xc0011021, value);
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}
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}
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cpu_detect_cache_sizes(c);
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/* Multi core CPU? */
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@ -656,33 +694,6 @@ static void init_amd(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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#ifdef CONFIG_X86_64
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if (c->x86 == 0x10) {
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/* do this for boot cpu */
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if (c == &boot_cpu_data)
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check_enable_amd_mmconf_dmi();
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fam10h_check_enable_mmcfg();
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}
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if (c == &boot_cpu_data && c->x86 >= 0xf) {
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unsigned long long tseg;
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/*
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* Split up direct mapping around the TSEG SMM area.
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* Don't do it for gbpages because there seems very little
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* benefit in doing so.
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*/
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if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
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unsigned long pfn = tseg >> PAGE_SHIFT;
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printk(KERN_DEBUG "tseg: %010llx\n", tseg);
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if (pfn_range_is_mapped(pfn, pfn + 1))
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set_memory_4k((unsigned long)__va(tseg), 1);
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}
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}
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#endif
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/*
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* Family 0x12 and above processors have APIC timer
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* running in deep C states.
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@ -690,34 +701,6 @@ static void init_amd(struct cpuinfo_x86 *c)
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if (c->x86 > 0x11)
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set_cpu_cap(c, X86_FEATURE_ARAT);
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if (c->x86 == 0x10) {
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/*
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* Disable GART TLB Walk Errors on Fam10h. We do this here
|
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* because this is always needed when GART is enabled, even in a
|
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* kernel which has no MCE support built in.
|
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* BIOS should disable GartTlbWlk Errors already. If
|
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* it doesn't, do it here as suggested by the BKDG.
|
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*
|
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* Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
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*/
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msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
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/*
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* On family 10h BIOS may not have properly enabled WC+ support,
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* causing it to be converted to CD memtype. This may result in
|
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* performance degradation for certain nested-paging guests.
|
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* Prevent this conversion by clearing bit 24 in
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* MSR_AMD64_BU_CFG2.
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*
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* NOTE: we want to use the _safe accessors so as not to #GP kvm
|
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* guests on older kvm hosts.
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*/
|
||||
msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
|
||||
|
||||
if (cpu_has_amd_erratum(c, amd_erratum_383))
|
||||
set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
|
||||
}
|
||||
|
||||
if (cpu_has_amd_erratum(c, amd_erratum_400))
|
||||
set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue