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drm/amd/display: fix workaround for incorrect double buffer register for DLG ADL and TTU 

[ Upstream commit 85e148fb96 ]

[Why]
these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values
whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern.

[How]
there is a driver bug where we don't check for 0, which is uninitialzed HW default.  since 0 is smaller than any value we need to program,
driver end up with not programming these registers

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
5.4-rM2-2.2.x-imx-squashed
Tony Cheng 2020-01-28 16:00:22 +08:00 committed by Greg Kroah-Hartman
parent 1f483c3ef0
commit 26eae6def7
1 changed files with 25 additions and 10 deletions
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35
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
View File

@ -73,32 +73,47 @@ void apply_DEDCN21_142_wa_for_hostvm_deadline(
struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
{
struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
uint32_t cur_value;
uint32_t refcyc_per_vm_group_vblank;
uint32_t refcyc_per_vm_req_vblank;
uint32_t refcyc_per_vm_group_flip;
uint32_t refcyc_per_vm_req_flip;
const uint32_t uninitialized_hw_default = 0;
REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
REG_GET(VBLANK_PARAMETERS_5,
REFCYC_PER_VM_GROUP_VBLANK, &refcyc_per_vm_group_vblank);
if (refcyc_per_vm_group_vblank == uninitialized_hw_default ||
refcyc_per_vm_group_vblank > dlg_attr->refcyc_per_vm_group_vblank)
REG_SET(VBLANK_PARAMETERS_5, 0,
REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
REG_GET(VBLANK_PARAMETERS_6,
REFCYC_PER_VM_REQ_VBLANK,
&cur_value);
if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
REFCYC_PER_VM_REQ_VBLANK, &refcyc_per_vm_req_vblank);
if (refcyc_per_vm_req_vblank == uninitialized_hw_default ||
refcyc_per_vm_req_vblank > dlg_attr->refcyc_per_vm_req_vblank)
REG_SET(VBLANK_PARAMETERS_6, 0,
REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
REG_GET(FLIP_PARAMETERS_3,
REFCYC_PER_VM_GROUP_FLIP, &refcyc_per_vm_group_flip);
if (refcyc_per_vm_group_flip == uninitialized_hw_default ||
refcyc_per_vm_group_flip > dlg_attr->refcyc_per_vm_group_flip)
REG_SET(FLIP_PARAMETERS_3, 0,
REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
REG_GET(FLIP_PARAMETERS_4,
REFCYC_PER_VM_REQ_FLIP, &refcyc_per_vm_req_flip);
if (refcyc_per_vm_req_flip == uninitialized_hw_default ||
refcyc_per_vm_req_flip > dlg_attr->refcyc_per_vm_req_flip)
REG_SET(FLIP_PARAMETERS_4, 0,
REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
REG_SET(FLIP_PARAMETERS_5, 0,
REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
REG_SET(FLIP_PARAMETERS_6, 0,
REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
}