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drm: omapdrm: dss: Pass PLL pointer to dss_ctrl_pll_enable()

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This will allow accessing the PLL data to get the DSS device pointer,
removing the need to access the global DSS private data.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
This commit is contained in:
Laurent Pinchart 2018-02-13 14:00:22 +02:00 committed by Tomi Valkeinen
parent 7b295257a1
commit 2726099921
4 changed files with 13 additions and 12 deletions
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13
drivers/gpu/drm/omapdrm/dss/dss.c
View file

@ -152,17 +152,17 @@ static void dss_restore_context(void)
#undef SR #undef SR
#undef RR #undef RR
void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable)
{ {
unsigned int shift; unsigned int shift;
unsigned int val; unsigned int val;
if (!dss.syscon_pll_ctrl) if (!pll->dss->syscon_pll_ctrl)
return; return;
val = !enable; val = !enable;
switch (pll_id) { switch (pll->id) {
case DSS_PLL_VIDEO1: case DSS_PLL_VIDEO1:
shift = 0; shift = 0;
break; break;
@ -173,12 +173,13 @@ void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
shift = 2; shift = 2;
break; break;
default: default:
DSSERR("illegal DSS PLL ID %d\n", pll_id); DSSERR("illegal DSS PLL ID %d\n", pll->id);
return; return;
} }
regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, regmap_update_bits(pll->dss->syscon_pll_ctrl,
1 << shift, val << shift); pll->dss->syscon_pll_ctrl_offset,
1 << shift, val << shift);
} }
static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src,

2
drivers/gpu/drm/omapdrm/dss/dss.h
View file

@ -310,7 +310,7 @@ struct dss_pll *dss_video_pll_init(struct dss_device *dss,
struct regulator *regulator); struct regulator *regulator);
void dss_video_pll_uninit(struct dss_pll *pll); void dss_video_pll_uninit(struct dss_pll *pll);
void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
void dss_sdi_init(int datapairs); void dss_sdi_init(int datapairs);
int dss_sdi_enable(void); int dss_sdi_enable(void);

4
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
View file

@ -48,7 +48,7 @@ static int hdmi_pll_enable(struct dss_pll *dsspll)
r = pm_runtime_get_sync(&pll->pdev->dev); r = pm_runtime_get_sync(&pll->pdev->dev);
WARN_ON(r < 0); WARN_ON(r < 0);
dss_ctrl_pll_enable(DSS_PLL_HDMI, true); dss_ctrl_pll_enable(dsspll, true);
r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
if (r) if (r)
@ -65,7 +65,7 @@ static void hdmi_pll_disable(struct dss_pll *dsspll)
hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
dss_ctrl_pll_enable(DSS_PLL_HDMI, false); dss_ctrl_pll_enable(dsspll, false);
r = pm_runtime_put_sync(&pll->pdev->dev); r = pm_runtime_put_sync(&pll->pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS); WARN_ON(r < 0 && r != -ENOSYS);

6
drivers/gpu/drm/omapdrm/dss/video-pll.c
View file

@ -68,7 +68,7 @@ static int dss_video_pll_enable(struct dss_pll *pll)
if (r) if (r)
return r; return r;
dss_ctrl_pll_enable(pll->id, true); dss_ctrl_pll_enable(pll, true);
dss_dpll_enable_scp_clk(vpll); dss_dpll_enable_scp_clk(vpll);
@ -82,7 +82,7 @@ static int dss_video_pll_enable(struct dss_pll *pll)
err_reset: err_reset:
dss_dpll_disable_scp_clk(vpll); dss_dpll_disable_scp_clk(vpll);
dss_ctrl_pll_enable(pll->id, false); dss_ctrl_pll_enable(pll, false);
dss_runtime_put(pll->dss); dss_runtime_put(pll->dss);
return r; return r;
@ -96,7 +96,7 @@ static void dss_video_pll_disable(struct dss_pll *pll)
dss_dpll_disable_scp_clk(vpll); dss_dpll_disable_scp_clk(vpll);
dss_ctrl_pll_enable(pll->id, false); dss_ctrl_pll_enable(pll, false);
dss_runtime_put(pll->dss); dss_runtime_put(pll->dss);
} }