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clk: imx8qxp: add enet RMII reference clock 

Add enet0/1 RMII mode reference clock support.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Fugang Duan 2019-07-09 16:52:05 +08:00 committed by Dong Aisheng
parent b184aa2ba9
commit 2777135445
2 changed files with 5 additions and 1 deletions
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2
drivers/clk/imx/clk-imx8qxp.c
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@ -142,11 +142,13 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_CONN_ENET0_RGMII_TXC_SEL] = imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
clks[IMX_CONN_ENET0_RGMII_RX_CLK] = imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
clks[IMX_CONN_LPCG_ENET0_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet0_ref_50_clk", NULL, IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
clks[IMX_CONN_ENET1_REF_DIV] = imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
clks[IMX_CONN_ENET1_RGMII_TXC_SEL] = imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
clks[IMX_CONN_ENET1_RGMII_RX_CLK] = imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
clks[IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK] = imx_clk_scu3("enet1_ref_50_clk", NULL, IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);

4
include/dt-bindings/clock/imx8-clock.h
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@ -317,8 +317,10 @@
#define IMX_CONN_LPCG_ENET0_TXC_SAMPLING_CLK 26
#define IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK 27
#define IMX_CONN_LPCG_ENET0_RMII_REF_50MHZ_CLK 28
#define IMX_CONN_LPCG_ENET1_RMII_REF_50MHZ_CLK 29
#define IMX_CONN_LPCG_CLK_END 28
#define IMX_CONN_LPCG_CLK_END 30
/* ADMA SS LPCG */
#define IMX_ADMA_LPCG_UART0_IPG_CLK 0