mtd: nand: add NAND driver "library" for Broadcom STB NAND controller
This core originated in Set-Top Box chips (BCM7xxx) but is used in a variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it to those architectures. There are multiple revisions of this core throughout the years, and almost every version broke register compatibility in some small way, but with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0, and v7.1. It's been tested on v5.0, v6.0, v6.1, v7.0, and v7.1 recently, so there hopefully are no more lurking inconsistencies. This patch adds just some library support, on which platform drivers can be built. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -394,6 +394,14 @@ config MTD_NAND_GPMI_NAND
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block, such as SD card. So pay attention to it when you enable
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block, such as SD card. So pay attention to it when you enable
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the GPMI.
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the GPMI.
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config MTD_NAND_BRCMNAND
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tristate "Broadcom STB NAND controller"
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depends on ARM || MIPS
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help
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Enables the Broadcom NAND controller driver. The controller was
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originally designed for Set-Top Box but is used on various BCM7xxx,
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BCM3xxx, BCM63xxx, iProc/Cygnus and more.
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config MTD_NAND_BCM47XXNFLASH
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config MTD_NAND_BCM47XXNFLASH
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tristate "Support for NAND flash on BCM4706 BCMA bus"
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tristate "Support for NAND flash on BCM4706 BCMA bus"
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depends on BCMA_NFLASH
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depends on BCMA_NFLASH
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@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
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obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
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obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
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obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
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obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
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obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
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nand-objs := nand_base.o nand_bbt.o nand_timings.o
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nand-objs := nand_base.o nand_bbt.o nand_timings.o
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1
drivers/mtd/nand/brcmnand/Makefile
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drivers/mtd/nand/brcmnand/Makefile
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@ -0,0 +1 @@
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obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o
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2195
drivers/mtd/nand/brcmnand/brcmnand.c
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2195
drivers/mtd/nand/brcmnand/brcmnand.c
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File diff suppressed because it is too large
Load diff
58
drivers/mtd/nand/brcmnand/brcmnand.h
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58
drivers/mtd/nand/brcmnand/brcmnand.h
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@ -0,0 +1,58 @@
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/*
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* Copyright © 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __BRCMNAND_H__
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#define __BRCMNAND_H__
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#include <linux/types.h>
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#include <linux/io.h>
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struct platform_device;
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struct dev_pm_ops;
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struct brcmnand_soc {
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struct platform_device *pdev;
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void *priv;
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};
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static inline u32 brcmnand_readl(void __iomem *addr)
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{
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/*
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* MIPS endianness is configured by boot strap, which also reverses all
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* bus endianness (i.e., big-endian CPU + big endian bus ==> native
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* endian I/O).
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*
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* Other architectures (e.g., ARM) either do not support big endian, or
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* else leave I/O in little endian mode.
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*/
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN))
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return __raw_readl(addr);
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else
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return readl_relaxed(addr);
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}
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static inline void brcmnand_writel(u32 val, void __iomem *addr)
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{
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/* See brcmnand_readl() comments */
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN))
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__raw_writel(val, addr);
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else
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writel_relaxed(val, addr);
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}
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int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
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int brcmnand_remove(struct platform_device *pdev);
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extern const struct dev_pm_ops brcmnand_pm_ops;
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#endif /* __BRCMNAND_H__ */
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