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RDMA/cxgb4: Fix accounting for unsignaled SQ WRs to deal with wrap

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When determining how many WRs are completed with a signaled CQE,
correctly deal with queue wraps.

Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Vipul Pandya <vipul@chelsio.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
This commit is contained in:
Steve Wise 2013-08-06 21:04:36 +05:30 committed by Roland Dreier
parent 1cf24dcef4
commit 27ca34f54a
1 changed files with 5 additions and 2 deletions
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7
drivers/infiniband/hw/cxgb4/cq.c
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@ -611,9 +611,12 @@ proc_cqe:
* to the first unsignaled one, and idx points to the
* signaled one. So adjust in_use based on this delta.
* if this is not completing any unsigned wrs, then the
* delta will be 0.
* delta will be 0. Handle wrapping also!
*/
wq->sq.in_use -= idx - wq->sq.cidx;
if (idx < wq->sq.cidx)
wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
else
wq->sq.in_use -= idx - wq->sq.cidx;
BUG_ON(wq->sq.in_use < 0 && wq->sq.in_use < wq->sq.size);
wq->sq.cidx = (uint16_t)idx;