crypto: caam - add support for SEC v5.x RNG4
The SEC v4.x' RNGB h/w block self-initialized. RNG4, available on SEC versions 5 and beyond, is based on a different standard that requires manual initialization. Also update any new errors From the SEC v5.2 reference manual: The SEC v5.2's RNG4 unit reuses some error IDs, thus the addition of rng_err_id_list over the CHA-independent err_id_list. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>hifive-unleashed-5.1
Kim Phillips
Herbert Xu
parent
e13af18a3e
commit
281922a1d4
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@ -2,13 +2,15 @@
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* CAAM control-plane driver backend
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* Controller-level driver, kernel property detection, initialization
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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*/
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#include "compat.h"
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#include "regs.h"
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#include "intern.h"
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#include "jr.h"
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#include "desc_constr.h"
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#include "error.h"
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static int caam_remove(struct platform_device *pdev)
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{
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@ -43,10 +45,120 @@ static int caam_remove(struct platform_device *pdev)
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return ret;
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}
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/*
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* Descriptor to instantiate RNG State Handle 0 in normal mode and
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* load the JDKEK, TDKEK and TDSK registers
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*/
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static void build_instantiation_desc(u32 *desc)
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{
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u32 *jump_cmd;
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init_job_desc(desc, 0);
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/* INIT RNG in non-test mode */
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append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
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OP_ALG_AS_INIT);
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/* wait for done */
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jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
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set_jump_tgt_here(desc, jump_cmd);
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/*
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* load 1 to clear written reg:
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* resets the done interrrupt and returns the RNG to idle.
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*/
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append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
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/* generate secure keys (non-test) */
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append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
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OP_ALG_RNG4_SK);
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}
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struct instantiate_result {
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struct completion completion;
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int err;
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};
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static void rng4_init_done(struct device *dev, u32 *desc, u32 err,
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void *context)
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{
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struct instantiate_result *instantiation = context;
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if (err) {
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char tmp[CAAM_ERROR_STR_MAX];
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dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
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}
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instantiation->err = err;
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complete(&instantiation->completion);
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}
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static int instantiate_rng(struct device *jrdev)
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{
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struct instantiate_result instantiation;
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dma_addr_t desc_dma;
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u32 *desc;
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int ret;
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desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA);
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if (!desc) {
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dev_err(jrdev, "cannot allocate RNG init descriptor memory\n");
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return -ENOMEM;
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}
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build_instantiation_desc(desc);
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desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE);
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init_completion(&instantiation.completion);
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ret = caam_jr_enqueue(jrdev, desc, rng4_init_done, &instantiation);
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if (!ret) {
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wait_for_completion_interruptible(&instantiation.completion);
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ret = instantiation.err;
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if (ret)
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dev_err(jrdev, "unable to instantiate RNG\n");
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}
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dma_unmap_single(jrdev, desc_dma, desc_bytes(desc), DMA_TO_DEVICE);
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kfree(desc);
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return ret;
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}
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/*
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* By default, the TRNG runs for 200 clocks per sample;
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* 800 clocks per sample generates better entropy.
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*/
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static void kick_trng(struct platform_device *pdev)
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{
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struct device *ctrldev = &pdev->dev;
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struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
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struct caam_full __iomem *topregs;
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struct rng4tst __iomem *r4tst;
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u32 val;
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topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
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r4tst = &topregs->ctrl.r4tst[0];
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/* put RNG4 into program mode */
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setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
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/* 800 clocks per sample */
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val = rd_reg32(&r4tst->rtsdctl);
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val = (val & ~RTSDCTL_ENT_DLY_MASK) | (800 << RTSDCTL_ENT_DLY_SHIFT);
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wr_reg32(&r4tst->rtsdctl, val);
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/* min. freq. count */
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wr_reg32(&r4tst->rtfrqmin, 400);
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/* max. freq. count */
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wr_reg32(&r4tst->rtfrqmax, 6400);
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/* put RNG4 into run mode */
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clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
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}
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/* Probe routine for CAAM top (controller) level */
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static int caam_probe(struct platform_device *pdev)
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{
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int ring, rspec;
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int ret, ring, rspec;
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struct device *dev;
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struct device_node *nprop, *np;
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struct caam_ctrl __iomem *ctrl;
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@ -146,6 +258,19 @@ static int caam_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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/*
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* RNG4 based SECs (v5+) need special initialization prior
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* to executing any descriptors
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*/
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if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) {
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kick_trng(pdev);
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ret = instantiate_rng(ctrlpriv->jrdev[0]);
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if (ret) {
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caam_remove(pdev);
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return ret;
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}
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}
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/* NOTE: RTIC detection ought to go here, around Si time */
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/* Initialize queue allocator lock */
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@ -1172,6 +1172,11 @@ struct sec4_sg_entry {
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#define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT)
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#define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT)
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/* RNG4 set */
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#define OP_ALG_RNG4_SHIFT 4
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#define OP_ALG_RNG4_MASK (0x1f3 << OP_ALG_RNG4_SHIFT)
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#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
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#define OP_ALG_AS_SHIFT 2
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#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT)
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@ -39,18 +39,20 @@ static void report_ccb_status(u32 status, char *outstr)
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char *cha_id_list[] = {
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"",
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"AES",
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"DES, 3DES",
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"DES",
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"ARC4",
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"MD5, SHA-1, SH-224, SHA-256, SHA-384, SHA-512",
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"MDHA",
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"RNG",
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"SNOW f8",
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"Kasumi f8, f9",
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"All Public Key Algorithms",
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"CRC",
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"Kasumi f8/9",
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"PKHA",
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"CRCA",
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"SNOW f9",
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"ZUCE",
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"ZUCA",
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};
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char *err_id_list[] = {
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"None. No error.",
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"No error.",
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"Mode error.",
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"Data size error.",
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"Key size error.",
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@ -67,6 +69,20 @@ static void report_ccb_status(u32 status, char *outstr)
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"Invalid CHA combination was selected",
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"Invalid CHA selected.",
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};
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char *rng_err_id_list[] = {
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"",
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"",
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"",
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"Instantiate",
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"Not instantiated",
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"Test instantiate",
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"Prediction resistance",
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"",
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"Prediction resistance and test request",
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"Uninstantiate",
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"",
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"Secure key generation",
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};
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u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >>
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JRSTA_CCBERR_CHAID_SHIFT;
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u8 err_id = status & JRSTA_CCBERR_ERRID_MASK;
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@ -81,7 +97,13 @@ static void report_ccb_status(u32 status, char *outstr)
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cha_id, sizeof("ff"));
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}
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if (err_id < ARRAY_SIZE(err_id_list)) {
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if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG &&
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err_id < ARRAY_SIZE(rng_err_id_list) &&
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strlen(rng_err_id_list[err_id])) {
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/* RNG-only error */
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SPRINTFCAT(outstr, "%s", rng_err_id_list[err_id],
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strlen(rng_err_id_list[err_id]));
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} else if (err_id < ARRAY_SIZE(err_id_list)) {
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SPRINTFCAT(outstr, "%s", err_id_list[err_id],
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strlen(err_id_list[err_id]));
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} else {
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@ -101,10 +123,10 @@ static void report_deco_status(u32 status, char *outstr)
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u8 value;
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char *error_text;
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} desc_error_list[] = {
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{ 0x00, "None. No error." },
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{ 0x00, "No error." },
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{ 0x01, "SGT Length Error. The descriptor is trying to read "
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"more data than is contained in the SGT table." },
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{ 0x02, "Reserved." },
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{ 0x02, "SGT Null Entry Error." },
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{ 0x03, "Job Ring Control Error. There is a bad value in the "
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"Job Ring Control register." },
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{ 0x04, "Invalid Descriptor Command. The Descriptor Command "
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@ -116,7 +138,7 @@ static void report_deco_status(u32 status, char *outstr)
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{ 0x09, "Invalid OPERATION Command" },
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{ 0x0A, "Invalid FIFO LOAD Command" },
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{ 0x0B, "Invalid FIFO STORE Command" },
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{ 0x0C, "Invalid MOVE Command" },
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{ 0x0C, "Invalid MOVE/MOVE_LEN Command" },
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{ 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is "
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"invalid because the target is not a Job Header "
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"Command, or the jump is from a Trusted Descriptor to "
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@ -166,6 +188,8 @@ static void report_deco_status(u32 status, char *outstr)
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"(input frame; block ciphers) and IPsec decap (output "
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"frame, when doing the next header byte update) and "
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"DCRC (output frame)." },
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{ 0x23, "Read Input Frame error" },
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{ 0x24, "JDKEK, TDKEK or TDSK not loaded error" },
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{ 0x80, "DNR (do not run) error" },
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{ 0x81, "undefined protocol command" },
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{ 0x82, "invalid setting in PDB" },
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@ -167,7 +167,7 @@ struct partid {
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u32 pidr; /* partition ID, DECO */
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};
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/* RNG test mode (replicated twice in some configurations) */
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/* RNGB test mode (replicated twice in some configurations) */
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/* Padded out to 0x100 */
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struct rngtst {
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u32 mode; /* RTSTMODEx - Test mode */
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@ -200,6 +200,31 @@ struct rngtst {
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u32 rsvd14[15];
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};
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/* RNG4 TRNG test registers */
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struct rng4tst {
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#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
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u32 rtmctl; /* misc. control register */
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u32 rtscmisc; /* statistical check misc. register */
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u32 rtpkrrng; /* poker range register */
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union {
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u32 rtpkrmax; /* PRGM=1: poker max. limit register */
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u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
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};
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#define RTSDCTL_ENT_DLY_SHIFT 16
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#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
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u32 rtsdctl; /* seed control register */
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union {
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u32 rtsblim; /* PRGM=1: sparse bit limit register */
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u32 rttotsam; /* PRGM=0: total samples register */
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};
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u32 rtfrqmin; /* frequency count min. limit register */
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union {
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u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
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u32 rtfrqcnt; /* PRGM=0: freq. count register */
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};
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u32 rsvd1[56];
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};
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/*
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* caam_ctrl - basic core configuration
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* starts base + 0x0000 padded out to 0x1000
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@ -249,7 +274,10 @@ struct caam_ctrl {
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/* RNG Test/Verification/Debug Access 600-7ff */
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/* (Useful in Test/Debug modes only...) */
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struct rngtst rtst[2];
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union {
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struct rngtst rtst[2];
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struct rng4tst r4tst[2];
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};
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u32 rsvd9[448];
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