Merge branches 'clk-unisoc', 'clk-tegra', 'clk-qcom' and 'clk-imx' into clk-next
- Add support for Unisoc SC9863A clks - GPU GX GDSC support on Qualcomm sc7180 - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support * clk-unisoc: clk: sprd: fix to get a correct ibias of pll clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks * clk-tegra: clk: tegra: Use NULL for pointer initialization clk: tegra: Remove audio clocks configuration from clock driver clk: tegra: Remove tegra_pmc_clk_init along with clk ids clk: tegra: Remove CLK_M_DIV fixed clocks clk: tegra: Fix Tegra PMC clock out parents clk: tegra: Add Tegra OSC to clock lookup clk: tegra: Add support for OSC_DIV fixed clocks dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks * clk-qcom: (21 commits) clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 ipq806x: gcc: Added the enable regs and mask for PRNG clk: qcom: Add modem clock controller driver for SC7180 clk: qcom: gcc: Add support for modem clocks in GCC dt-bindings: clock: Add YAML schemas for the QCOM MSS clock bindings clk: qcom: clk-rpm: add missing rpm clk for ipq806x clk: qcom: gcc: Add global clock controller driver for SM8250 dt-bindings: clock: Add SM8250 GCC clock bindings clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs clk: qcom: clk-alpha-pll: Refactor trion PLL clk: qcom: clk-alpha-pll: Use common names for defines dt-bindings: clock: rpmcc: Document msm8976 compatible clk: qcom: smd: Add support for MSM8976 rpm clocks clk: qcom: clk-rpmh: Wait for completion when enabling clocks clk: qcom: rpmh: Add support for RPMH clocks on SM8250 dt-bindings: clock: Add RPMHCC bindings for SM8250 clk: qcom: alpha-pll: Make error prints more informative clk: qcom: gpucc: Add support for GX GDSC for SC7180 ... * clk-imx: (43 commits) dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: imx: clk-gate2: Pass the device to the register function clk: imx7d: Add PXP clock clk: imx8mq: A53 core clock no need to be critical clk: imx8mp: A53 core clock no need to be critical clk: imx8mm: A53 core clock no need to be critical clk: imx8mn: A53 core clock no need to be critical clk: imx: pllv4: use prepare/unprepare clk: imx: pfdv2: determine best parent rate clk: imx: pfdv2: switch to use determine_rate clk: imx: Fix division by zero warning on pfdv2 clk: imx: clk-sscg-pll: Drop unnecessary initialization clk: imx: pll14xx: Return error if pll type is invalid clk: imx: imx8mp: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mq: fix a53 cpu clock clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock clk: imx8mn: Remove unused includes ...
This commit is contained in:
commit
28ecaf1c30
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@ -1,300 +0,0 @@
|
|||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
== Power Management Controller Node ==
|
||||
|
||||
The PMC block interacts with an external Power Management Unit. The PMC
|
||||
mostly controls the entry and exit of the system from different sleep
|
||||
modes. It provides power-gating controllers for SoC and CPU power-islands.
|
||||
|
||||
Required properties:
|
||||
- name : Should be pmc
|
||||
- compatible : Should contain one of the following:
|
||||
For Tegra20 must contain "nvidia,tegra20-pmc".
|
||||
For Tegra30 must contain "nvidia,tegra30-pmc".
|
||||
For Tegra114 must contain "nvidia,tegra114-pmc"
|
||||
For Tegra124 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra132 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra210 must contain "nvidia,tegra210-pmc"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names : Must include the following entries:
|
||||
"pclk" (The Tegra clock of that name),
|
||||
"clk32k_in" (The 32KHz clock input to Tegra).
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and then
|
||||
fed into the ARM GIC. The PMC is not involved in the detection or
|
||||
handling of this interrupt signal, merely its inversion.
|
||||
- nvidia,suspend-mode : The suspend mode that the platform should use.
|
||||
Valid values are 0, 1 and 2:
|
||||
0 (LP0): CPU + Core voltage off and DRAM in self-refresh
|
||||
1 (LP1): CPU voltage off and DRAM in self-refresh
|
||||
2 (LP2): CPU voltage off
|
||||
- nvidia,core-power-req-active-high : Boolean, core power request active-high
|
||||
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
|
||||
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
|
||||
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
|
||||
is enabled.
|
||||
|
||||
Required properties when nvidia,suspend-mode is specified:
|
||||
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
|
||||
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
|
||||
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uS.
|
||||
- nvidia,core-pwr-off-time : Core power off time in uS.
|
||||
|
||||
Required properties when nvidia,suspend-mode=<0>:
|
||||
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
|
||||
The LP0 vector contains the warm boot code that is executed by AVP when
|
||||
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
|
||||
processor and always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed from the deep
|
||||
sleep mode, the warm boot code will restore some PLLs, clocks and then
|
||||
bring up CPU0 for resuming the system.
|
||||
|
||||
Hardware-triggered thermal reset:
|
||||
On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
|
||||
hardware-triggered thermal reset will be enabled.
|
||||
|
||||
Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
|
||||
- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
|
||||
described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
|
||||
Tegra K1 Technical Reference Manual.
|
||||
- nvidia,bus-addr : Bus address of the PMU on the I2C bus
|
||||
- nvidia,reg-addr : I2C register address to write poweroff command to
|
||||
- nvidia,reg-data : Poweroff command to write to PMU
|
||||
|
||||
Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
|
||||
- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
Optional nodes:
|
||||
- powergates : This node contains a hierarchy of power domain nodes, which
|
||||
should match the powergates on the Tegra SoC. See "Powergate
|
||||
Nodes" below.
|
||||
|
||||
Example:
|
||||
|
||||
/ SoC dts including file
|
||||
pmc@7000f400 {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car 110>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
nvidia,cpu-pwr-off-time = <100>;
|
||||
nvidia,core-pwr-good-time = <3845 3845>;
|
||||
nvidia,core-pwr-off-time = <458>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
nvidia,lp0-vec = <0xbdffd000 0x2000>;
|
||||
};
|
||||
|
||||
/ Tegra board dts file
|
||||
{
|
||||
...
|
||||
pmc@7000f400 {
|
||||
i2c-thermtrip {
|
||||
nvidia,i2c-controller-id = <4>;
|
||||
nvidia,bus-addr = <0x40>;
|
||||
nvidia,reg-addr = <0x36>;
|
||||
nvidia,reg-data = <0x2>;
|
||||
};
|
||||
};
|
||||
...
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
|
||||
== Powergate Nodes ==
|
||||
|
||||
Each of the powergate nodes represents a power-domain on the Tegra SoC
|
||||
that can be power-gated by the Tegra PMC. The name of the powergate node
|
||||
should be one of the below. Note that not every powergate is applicable
|
||||
to all Tegra devices and the following list shows which powergates are
|
||||
applicable to which devices. Please refer to the Tegra TRM for more
|
||||
details on the various powergates.
|
||||
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
Required properties:
|
||||
- clocks: Must contain an entry for each clock required by the PMC for
|
||||
controlling a power-gate. See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each reset required by the PMC for
|
||||
controlling a power-gate. See ../reset/reset.txt for details.
|
||||
- #power-domain-cells: Must be 0.
|
||||
|
||||
Example:
|
||||
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
== Powergate Clients ==
|
||||
|
||||
Hardware blocks belonging to a power domain should contain a "power-domains"
|
||||
property that is a phandle pointing to the corresponding powergate node.
|
||||
|
||||
Example:
|
||||
|
||||
adma: adma@702e2000 {
|
||||
...
|
||||
power-domains = <&pd_audio>;
|
||||
...
|
||||
};
|
||||
|
||||
== Pad Control ==
|
||||
|
||||
On Tegra SoCs a pad is a set of pins which are configured as a group.
|
||||
The pin grouping is a fixed attribute of the hardware. The PMC can be
|
||||
used to set pad power state and signaling voltage. A pad can be either
|
||||
in active or power down mode. The support for power state and signaling
|
||||
voltage configuration varies depending on the pad in question. 3.3 V and
|
||||
1.8 V signaling voltages are supported on pins where software
|
||||
controllable signaling voltage switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132:
|
||||
audio bb cam comp
|
||||
csia csb cse dsi
|
||||
dsib dsic dsid hdmi
|
||||
hsic hv lvds mipi-bias
|
||||
nand pex-bias pex-clk1 pex-clk2
|
||||
pex-cntrl sdmmc1 sdmmc3 sdmmc4
|
||||
sys_ddc uart usb0 usb1
|
||||
usb2 usb_bias
|
||||
|
||||
The following pads are present on Tegra210:
|
||||
audio audio-hv cam csia
|
||||
csib csic csid csie
|
||||
csif dbg debug-nonao dmic
|
||||
dp dsi dsib dsic
|
||||
dsid emmc emmc2 gpio
|
||||
hdmi hsic lvds mipi-bias
|
||||
pex-bias pex-clk1 pex-clk2 pex-cntrl
|
||||
sdmmc1 sdmmc3 spi spi-hv
|
||||
uart usb0 usb1 usb2
|
||||
usb3 usb-bias
|
||||
|
||||
Required pin configuration properties:
|
||||
- pins: Must contain name of the pad(s) to be configured.
|
||||
|
||||
Optional pin configuration properties:
|
||||
- low-power-enable: Configure the pad into power down mode
|
||||
- low-power-disable: Configure the pad into active mode
|
||||
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
|
||||
or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
|
||||
Note: The power state can be configured on all of the Tegra124 and
|
||||
Tegra132 pads. None of the Tegra124 or Tegra132 pads support
|
||||
signaling voltage switching.
|
||||
|
||||
Note: All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported on
|
||||
following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
|
||||
pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
Pad configuration state example:
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
...
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
hdmi_off: hdmi-off {
|
||||
pins = "hdmi";
|
||||
low-power-enable;
|
||||
}
|
||||
|
||||
hdmi_on: hdmi-on {
|
||||
pins = "hdmi";
|
||||
low-power-disable;
|
||||
}
|
||||
};
|
||||
|
||||
Pinctrl client example:
|
||||
sdmmc1: sdhci@700b0000 {
|
||||
...
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
};
|
||||
...
|
||||
sor@54540000 {
|
||||
...
|
||||
pinctrl-0 = <&hdmi_off>;
|
||||
pinctrl-1 = <&hdmi_on>;
|
||||
pinctrl-names = "hdmi-on", "hdmi-off";
|
||||
};
|
|
@ -0,0 +1,354 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Tegra Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra20-pmc
|
||||
- nvidia,tegra30-pmc
|
||||
- nvidia,tegra114-pmc
|
||||
- nvidia,tegra124-pmc
|
||||
- nvidia,tegra210-pmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description:
|
||||
Offset and length of the register set for the device.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: clk32k_in
|
||||
description:
|
||||
Must includes entries pclk and clk32k_in.
|
||||
pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
|
||||
input to Tegra.
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
description:
|
||||
Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clocks-bindings.txt for details.
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
|
||||
PMC also has blink control which allows 32Khz clock output to
|
||||
Tegra blink pad.
|
||||
Consumer of PMC clock should specify the desired clock by having
|
||||
the clock ID in its "clocks" phandle cell with pmc clock provider.
|
||||
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
|
||||
clock IDs.
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
description:
|
||||
Specifies number of cells needed to encode an interrupt source.
|
||||
The value must be 2.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
nvidia,invert-interrupt:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Inverts the PMU interrupt signal.
|
||||
The PMU is an external Power Management Unit, whose interrupt output
|
||||
signal is fed into the PMC. This signal is optionally inverted, and
|
||||
then fed into the ARM GIC. The PMC is not involved in the detection
|
||||
or handling of this interrupt signal, merely its inversion.
|
||||
|
||||
nvidia,core-power-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Core power request active-high.
|
||||
|
||||
nvidia,sys-clock-req-active-high:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: System clock request active-high.
|
||||
|
||||
nvidia,combined-power-req:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: combined power request for CPU and Core.
|
||||
|
||||
nvidia,cpu-pwr-good-en:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description:
|
||||
CPU power good signal from external PMIC to PMC is enabled.
|
||||
|
||||
nvidia,suspend-mode:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2]
|
||||
description:
|
||||
The suspend mode that the platform should use.
|
||||
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
|
||||
Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
|
||||
Mode 2 is for LP2, CPU voltage off
|
||||
|
||||
nvidia,cpu-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power good time in uSec.
|
||||
|
||||
nvidia,cpu-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: CPU power off time in uSec.
|
||||
|
||||
nvidia,core-pwr-good-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<Oscillator-stable-time Power-stable-time>
|
||||
Core power good time in uSec.
|
||||
|
||||
nvidia,core-pwr-off-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Core power off time in uSec.
|
||||
|
||||
nvidia,lp0-vec:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
<start length> Starting address and length of LP0 vector.
|
||||
The LP0 vector contains the warm boot code that is executed
|
||||
by AVP when resuming from the LP0 state.
|
||||
The AVP (Audio-Video Processor) is an ARM7 processor and
|
||||
always being the first boot processor when chip is power on
|
||||
or resume from deep sleep mode. When the system is resumed
|
||||
from the deep sleep mode, the warm boot code will restore
|
||||
some PLLs, clocks and then brings up CPU0 for resuming the
|
||||
system.
|
||||
|
||||
i2c-thermtrip:
|
||||
type: object
|
||||
description:
|
||||
On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
|
||||
hardware-triggered thermal reset will be enabled.
|
||||
|
||||
properties:
|
||||
nvidia,i2c-controller-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
ID of I2C controller to send poweroff command to PMU.
|
||||
Valid values are described in section 9.2.148
|
||||
"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
|
||||
Manual.
|
||||
|
||||
nvidia,bus-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Bus address of the PMU on the I2C bus.
|
||||
|
||||
nvidia,reg-addr:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: PMU I2C register address to issue poweroff command.
|
||||
|
||||
nvidia,reg-data:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Poweroff command to write to PMU.
|
||||
|
||||
nvidia,pinmux-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Pinmux used by the hardware when issuing Poweroff command.
|
||||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
required:
|
||||
- nvidia,i2c-controller-id
|
||||
- nvidia,bus-addr
|
||||
- nvidia,reg-addr
|
||||
- nvidia,reg-data
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
powergates:
|
||||
type: object
|
||||
description: |
|
||||
This node contains a hierarchy of power domain nodes, which should
|
||||
match the powergates on the Tegra SoC. Each powergate node
|
||||
represents a power-domain on the Tegra SoC that can be power-gated
|
||||
by the Tegra PMC.
|
||||
Hardware blocks belonging to a power domain should contain
|
||||
"power-domains" property that is a phandle pointing to corresponding
|
||||
powergate node.
|
||||
The name of the powergate node should be one of the below. Note that
|
||||
not every powergate is applicable to all Tegra devices and the following
|
||||
list shows which powergates are applicable to which devices.
|
||||
Please refer to Tegra TRM for mode details on the powergate nodes to
|
||||
use for each power-gate block inside Tegra.
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+$":
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each clock required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../clocks/clock-bindings.txt document for more details.
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
description:
|
||||
Must contain an entry for each reset required by the PMC
|
||||
for controlling a power-gate.
|
||||
See ../reset/reset.txt for more details.
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 0
|
||||
description: Must be 0.
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- resets
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"^[a-f0-9]+-[a-f0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
This is a Pad configuration node. On Tegra SOCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power state
|
||||
and signaling voltage. A pad can be either in active or power down mode.
|
||||
The support for power state and signaling voltage configuration varies
|
||||
depending on the pad in question. 3.3V and 1.8V signaling voltages
|
||||
are supported on pins where software controllable signaling voltage
|
||||
switching is available.
|
||||
|
||||
The pad configuration state nodes are placed under the pmc node and they
|
||||
are referred to by the pinctrl client properties. For more information
|
||||
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
The pad name should be used as the value of the pins property in pin
|
||||
configuration nodes.
|
||||
|
||||
The following pads are present on Tegra124 and Tegra132
|
||||
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
|
||||
hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
|
||||
sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
|
||||
|
||||
The following pads are present on Tegra210
|
||||
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
|
||||
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
|
||||
hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain name of the pad(s) to be configured.
|
||||
|
||||
low-power-enable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into power down mode.
|
||||
|
||||
low-power-disable:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: Configure the pad into active mode.
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
Power state can be configured on all Tegra124 and Tegra132
|
||||
pads. None of the Tegra124 or Tegra132 pads support signaling
|
||||
voltage switching.
|
||||
All of the listed Tegra210 pads except pex-cntrl support power
|
||||
state configuration. Signaling voltage switching is supported
|
||||
on below Tegra210 pads.
|
||||
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
|
||||
sdmmc3, spi, spi-hv, and uart.
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-names
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
dependencies:
|
||||
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
|
||||
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
|
||||
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/soc/tegra-pmc.h>
|
||||
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <0>;
|
||||
nvidia,cpu-pwr-good-time = <0>;
|
||||
nvidia,cpu-pwr-off-time = <0>;
|
||||
nvidia,core-pwr-good-time = <4587 3876>;
|
||||
nvidia,core-pwr-off-time = <39065>;
|
||||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
pd_xusbss: xusba {
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -1,29 +0,0 @@
|
|||
* Clock bindings for NXP i.MX8M Mini
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mm-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "osc_32k"
|
||||
- "osc_24m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
68
Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
Normal file
68
Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
Normal file
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Mini Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Mini clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mm-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc_32k
|
||||
- const: osc_24m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
|
||||
for the full list of i.MX8M Mini clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mm-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
|
@ -40,7 +40,7 @@ properties:
|
|||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description: |
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
|
||||
for the full list of i.MX8M Nano clock IDs.
|
||||
|
@ -57,7 +57,7 @@ examples:
|
|||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mn-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
|
||||
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
|
||||
|
@ -65,48 +65,4 @@ examples:
|
|||
"clk_ext2", "clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
# Required external clocks for Clock Control Module node:
|
||||
- |
|
||||
osc_32k: clock-osc-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "osc_32k";
|
||||
};
|
||||
|
||||
osc_24m: clock-osc-24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "osc_24m";
|
||||
};
|
||||
|
||||
clk_ext1: clock-ext1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext1";
|
||||
};
|
||||
|
||||
clk_ext2: clock-ext2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext2";
|
||||
};
|
||||
|
||||
clk_ext3: clock-ext3 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <133000000>;
|
||||
clock-output-names = "clk_ext3";
|
||||
};
|
||||
|
||||
clk_ext4: clock-ext4 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency= <133000000>;
|
||||
clock-output-names = "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
|
@ -1,20 +0,0 @@
|
|||
* Clock bindings for NXP i.MX8M Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8mq-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include the following entries:
|
||||
- "ckil"
|
||||
- "osc_25m"
|
||||
- "osc_27m"
|
||||
- "clk_ext1"
|
||||
- "clk_ext2"
|
||||
- "clk_ext3"
|
||||
- "clk_ext4"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
72
Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
Normal file
72
Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
Normal file
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Quad Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Quad clock control module is an integrated clock controller, which
|
||||
generates and supplies to all modules.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mq-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 25m osc
|
||||
- description: 27m osc
|
||||
- description: ext1 clock input
|
||||
- description: ext2 clock input
|
||||
- description: ext3 clock input
|
||||
- description: ext4 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc_25m
|
||||
- const: osc_27m
|
||||
- const: clk_ext1
|
||||
- const: clk_ext2
|
||||
- const: clk_ext3
|
||||
- const: clk_ext4
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
|
||||
for the full list of i.MX8M Quad clock IDs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
clk: clock-controller@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
|
||||
<&clk_ext1>, <&clk_ext2>,
|
||||
<&clk_ext3>, <&clk_ext4>;
|
||||
clock-names = "ckil", "osc_25m", "osc_27m",
|
||||
"clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4";
|
||||
};
|
||||
|
||||
...
|
72
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
Normal file
72
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
Normal file
|
@ -0,0 +1,72 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8250
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8250.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8250
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8250";
|
||||
reg = <0 0x00100000 0 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
|
@ -14,7 +14,9 @@ Required properties :
|
|||
"qcom,rpmcc-apq8060", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8976", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-ipq806x", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
|
|
|
@ -20,6 +20,7 @@ properties:
|
|||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
- qcom,sm8250-rpmh-clk
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
|
62
Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml
Normal file
62
Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml
Normal file
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Modem Clock Controller Binding for SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm modem clock control module which supports the clocks on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,mss-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sc7180-mss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: gcc_mss_mfab_axi clock from GCC
|
||||
- description: gcc_mss_nav_axi clock from GCC
|
||||
- description: gcc_mss_cfg_ahb clock from GCC
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: gcc_mss_mfab_axis
|
||||
- const: gcc_mss_nav_axi
|
||||
- const: cfg_ahb
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
clock-controller@41a8000 {
|
||||
compatible = "qcom,sc7180-mss";
|
||||
reg = <0 0x041a8000 0 0x8000>;
|
||||
clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
|
||||
<&gcc GCC_MSS_NAV_AXI_CLK>,
|
||||
<&gcc GCC_MSS_CFG_AHB_CLK>;
|
||||
clock-names = "gcc_mss_mfab_axis",
|
||||
"gcc_mss_nav_axi",
|
||||
"cfg_ahb";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
...
|
|
@ -1,4 +1,4 @@
|
|||
Spreadtrum Clock Binding
|
||||
Spreadtrum SC9860 Clock Binding
|
||||
------------------------
|
||||
|
||||
Required properties:
|
105
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
Normal file
105
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
Normal file
|
@ -0,0 +1,105 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2019 Unisoc Inc.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: SC9863A Clock Control Unit Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
compatible :
|
||||
enum:
|
||||
- sprd,sc9863a-ap-clk
|
||||
- sprd,sc9863a-aon-clk
|
||||
- sprd,sc9863a-apahb-gate
|
||||
- sprd,sc9863a-pmu-gate
|
||||
- sprd,sc9863a-aonapb-gate
|
||||
- sprd,sc9863a-pll
|
||||
- sprd,sc9863a-mpll
|
||||
- sprd,sc9863a-rpll
|
||||
- sprd,sc9863a-dpll
|
||||
- sprd,sc9863a-mm-gate
|
||||
- sprd,sc9863a-apapb-gate
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: |
|
||||
The input parent clock(s) phandle for this clock, only list fixed
|
||||
clocks which are declared in devicetree.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: ext-26m
|
||||
- const: ext-32k
|
||||
- const: ext-4m
|
||||
- const: rco-100m
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- sprd,sc9863a-ap-clk
|
||||
- sprd,sc9863a-aon-clk
|
||||
then:
|
||||
required:
|
||||
- reg
|
||||
|
||||
else:
|
||||
description: |
|
||||
Other SC9863a clock nodes should be the child of a syscon node in
|
||||
which compatible string shoule be:
|
||||
"sprd,sc9863a-glbregs", "syscon", "simple-mfd"
|
||||
|
||||
The 'reg' property for the clock node is also required if there is a sub
|
||||
range of registers for the clocks.
|
||||
|
||||
examples:
|
||||
- |
|
||||
ap_clk: clock-controller@21500000 {
|
||||
compatible = "sprd,sc9863a-ap-clk";
|
||||
reg = <0 0x21500000 0 0x1000>;
|
||||
clocks = <&ext_26m>, <&ext_32k>;
|
||||
clock-names = "ext-26m", "ext-32k";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ap_ahb_regs: syscon@20e00000 {
|
||||
compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
|
||||
reg = <0 0x20e00000 0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x20e00000 0x4000>;
|
||||
|
||||
apahb_gate: apahb-gate@0 {
|
||||
compatible = "sprd,sc9863a-apahb-gate";
|
||||
reg = <0x0 0x1020>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
|
@ -15,6 +15,7 @@
|
|||
#define PCG_PREDIV_MAX 8
|
||||
|
||||
#define PCG_DIV_SHIFT 0
|
||||
#define PCG_CORE_DIV_WIDTH 3
|
||||
#define PCG_DIV_WIDTH 6
|
||||
#define PCG_DIV_MAX 64
|
||||
|
||||
|
@ -91,7 +92,7 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
|
|||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
int prediv_value;
|
||||
int div_value;
|
||||
int ret;
|
||||
|
@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divider_ops = {
|
|||
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
||||
const char * const *parent_names,
|
||||
int num_parents, void __iomem *reg,
|
||||
u32 composite_flags,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
|
||||
|
@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||
struct clk_divider *div = NULL;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_mux *mux = NULL;
|
||||
const struct clk_ops *divider_ops;
|
||||
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
|
@ -150,8 +153,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||
|
||||
div_hw = &div->hw;
|
||||
div->reg = reg;
|
||||
div->shift = PCG_PREDIV_SHIFT;
|
||||
div->width = PCG_PREDIV_WIDTH;
|
||||
if (composite_flags & IMX_COMPOSITE_CORE) {
|
||||
div->shift = PCG_DIV_SHIFT;
|
||||
div->width = PCG_CORE_DIV_WIDTH;
|
||||
divider_ops = &clk_divider_ops;
|
||||
} else {
|
||||
div->shift = PCG_PREDIV_SHIFT;
|
||||
div->width = PCG_PREDIV_WIDTH;
|
||||
divider_ops = &imx8m_clk_composite_divider_ops;
|
||||
}
|
||||
|
||||
div->lock = &imx_ccm_lock;
|
||||
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
|
||||
|
||||
|
@ -166,8 +177,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux_hw, &clk_mux_ops, div_hw,
|
||||
&imx8m_clk_composite_divider_ops,
|
||||
gate_hw, &clk_gate_ops, flags);
|
||||
divider_ops, gate_hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(hw))
|
||||
goto fail;
|
||||
|
||||
|
|
|
@ -55,7 +55,7 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
|
||||
struct clk_divider *div = to_clk_divider(hw);
|
||||
unsigned int divider, value;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
divider = parent_rate / rate;
|
||||
|
|
|
@ -42,7 +42,7 @@ static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
{
|
||||
struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
|
|
|
@ -40,7 +40,7 @@ static int clk_gate2_enable(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_gate2 *gate = to_clk_gate2(hw);
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
|
@ -62,7 +62,7 @@ static void clk_gate2_disable(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_gate2 *gate = to_clk_gate2(hw);
|
||||
u32 reg;
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
||||
|
@ -101,7 +101,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
|
|||
static void clk_gate2_disable_unused(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate2 *gate = to_clk_gate2(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(gate->lock, flags);
|
||||
|
@ -154,7 +154,7 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
|
|||
gate->hw.init = &init;
|
||||
hw = &gate->hw;
|
||||
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
ret = clk_hw_register(dev, hw);
|
||||
if (ret) {
|
||||
kfree(gate);
|
||||
return ERR_PTR(ret);
|
||||
|
|
|
@ -208,6 +208,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
of_node_put(np);
|
||||
anatop_base = base;
|
||||
|
||||
hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
|
||||
|
|
|
@ -802,6 +802,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
hws[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_hw_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
|
||||
hws[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
|
||||
hws[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_hw_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
|
||||
hws[IMX7D_PXP_CLK] = imx_clk_hw_gate4("pxp_clk", "main_axi_root_clk", base + 0x44c0, 0);
|
||||
hws[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
|
||||
hws[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_hw_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
|
||||
hws[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_hw_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
|
||||
|
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
|
|
@ -4,12 +4,10 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mm-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -41,6 +39,8 @@ static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
|||
static const char *imx8mm_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
|
||||
"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mm_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char *imx8mm_m4_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "sys_pll1_266m",
|
||||
"sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
|
||||
|
||||
|
@ -283,8 +283,10 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
|
|||
|
||||
static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out",
|
||||
"vpu_pll", "sys_pll1_80m", };
|
||||
static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
|
||||
"audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
|
||||
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
|
||||
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
@ -322,6 +324,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base))
|
||||
return -ENOMEM;
|
||||
|
||||
|
@ -414,20 +417,30 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* Core Slice */
|
||||
hws[IMX8MM_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels));
|
||||
hws[IMX8MM_CLK_M4_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mm_m4_sels, ARRAY_SIZE(imx8mm_m4_sels));
|
||||
hws[IMX8MM_CLK_VPU_SRC] = imx_clk_hw_mux2("vpu_src", base + 0x8100, 24, 3, imx8mm_vpu_sels, ARRAY_SIZE(imx8mm_vpu_sels));
|
||||
hws[IMX8MM_CLK_GPU3D_SRC] = imx_clk_hw_mux2("gpu3d_src", base + 0x8180, 24, 3, imx8mm_gpu3d_sels, ARRAY_SIZE(imx8mm_gpu3d_sels));
|
||||
hws[IMX8MM_CLK_GPU2D_SRC] = imx_clk_hw_mux2("gpu2d_src", base + 0x8200, 24, 3, imx8mm_gpu2d_sels, ARRAY_SIZE(imx8mm_gpu2d_sels));
|
||||
hws[IMX8MM_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
hws[IMX8MM_CLK_M4_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
|
||||
hws[IMX8MM_CLK_VPU_CG] = imx_clk_hw_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
|
||||
hws[IMX8MM_CLK_GPU3D_CG] = imx_clk_hw_gate3("gpu3d_cg", "gpu3d_src", base + 0x8180, 28);
|
||||
hws[IMX8MM_CLK_GPU2D_CG] = imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", base + 0x8200, 28);
|
||||
hws[IMX8MM_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
hws[IMX8MM_CLK_M4_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
|
||||
hws[IMX8MM_CLK_VPU_DIV] = imx_clk_hw_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
|
||||
hws[IMX8MM_CLK_GPU3D_DIV] = imx_clk_hw_divider2("gpu3d_div", "gpu3d_cg", base + 0x8180, 0, 3);
|
||||
hws[IMX8MM_CLK_GPU2D_DIV] = imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg", base + 0x8200, 0, 3);
|
||||
|
||||
hws[IMX8MM_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mm_m4_sels, base + 0x8080);
|
||||
hws[IMX8MM_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mm_vpu_sels, base + 0x8100);
|
||||
hws[IMX8MM_CLK_GPU3D_CORE] = imx8m_clk_hw_composite_core("gpu3d_core", imx8mm_gpu3d_sels, base + 0x8180);
|
||||
hws[IMX8MM_CLK_GPU2D_CORE] = imx8m_clk_hw_composite_core("gpu2d_core", imx8mm_gpu2d_sels, base + 0x8200);
|
||||
|
||||
/* For backwards compatibility */
|
||||
hws[IMX8MM_CLK_M4_SRC] = hws[IMX8MM_CLK_M4_CORE];
|
||||
hws[IMX8MM_CLK_M4_CG] = hws[IMX8MM_CLK_M4_CORE];
|
||||
hws[IMX8MM_CLK_M4_DIV] = hws[IMX8MM_CLK_M4_CORE];
|
||||
hws[IMX8MM_CLK_VPU_SRC] = hws[IMX8MM_CLK_VPU_CORE];
|
||||
hws[IMX8MM_CLK_VPU_CG] = hws[IMX8MM_CLK_VPU_CORE];
|
||||
hws[IMX8MM_CLK_VPU_DIV] = hws[IMX8MM_CLK_VPU_CORE];
|
||||
hws[IMX8MM_CLK_GPU3D_SRC] = hws[IMX8MM_CLK_GPU3D_CORE];
|
||||
hws[IMX8MM_CLK_GPU3D_CG] = hws[IMX8MM_CLK_GPU3D_CORE];
|
||||
hws[IMX8MM_CLK_GPU3D_DIV] = hws[IMX8MM_CLK_GPU3D_CORE];
|
||||
hws[IMX8MM_CLK_GPU2D_SRC] = hws[IMX8MM_CLK_GPU2D_CORE];
|
||||
hws[IMX8MM_CLK_GPU2D_CG] = hws[IMX8MM_CLK_GPU2D_CORE];
|
||||
hws[IMX8MM_CLK_GPU2D_DIV] = hws[IMX8MM_CLK_GPU2D_CORE];
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels));
|
||||
|
||||
/* BUS */
|
||||
hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
|
||||
|
@ -504,6 +517,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mm_wdog_sels, base + 0xb900);
|
||||
hws[IMX8MM_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mm_wrclk_sels, base + 0xb980);
|
||||
hws[IMX8MM_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mm_clko1_sels, base + 0xba00);
|
||||
hws[IMX8MM_CLK_CLKO2] = imx8m_clk_hw_composite("clko2", imx8mm_clko2_sels, base + 0xba80);
|
||||
hws[IMX8MM_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core", imx8mm_dsi_core_sels, base + 0xbb00);
|
||||
hws[IMX8MM_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref", imx8mm_dsi_phy_sels, base + 0xbb80);
|
||||
hws[IMX8MM_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi", imx8mm_dsi_dbi_sels, base + 0xbc00);
|
||||
|
@ -564,7 +578,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
hws[IMX8MM_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
hws[IMX8MM_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
hws[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_div", base + 0x44f0, 0);
|
||||
hws[IMX8MM_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", base + 0x44f0, 0);
|
||||
hws[IMX8MM_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
hws[IMX8MM_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
hws[IMX8MM_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
|
@ -586,7 +600,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
|
||||
hws[IMX8MM_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
|
||||
hws[IMX8MM_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
|
||||
hws[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", base + 0x4660, 0);
|
||||
hws[IMX8MM_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", base + 0x4660, 0);
|
||||
hws[IMX8MM_CLK_CSI1_ROOT] = imx_clk_hw_gate4("csi1_root_clk", "csi1_core", base + 0x4650, 0);
|
||||
|
||||
hws[IMX8MM_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
|
||||
|
@ -594,11 +608,14 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
hws[IMX8MM_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL);
|
||||
|
||||
hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MM_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MM_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MM_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MM_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MM_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MM_SYS_PLL1_800M]->clk);
|
||||
hws[IMX8MM_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MM_CLK_END);
|
||||
|
||||
|
|
|
@ -4,12 +4,10 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -40,6 +38,8 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
|
|||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
|
@ -317,6 +317,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base)) {
|
||||
ret = -ENOMEM;
|
||||
goto unregister_hws;
|
||||
|
@ -413,15 +414,21 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* CORE */
|
||||
hws[IMX8MN_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels));
|
||||
hws[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_hw_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels));
|
||||
hws[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_hw_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels));
|
||||
hws[IMX8MN_CLK_A53_CG] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28);
|
||||
hws[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_hw_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
hws[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_hw_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
hws[IMX8MN_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
hws[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_hw_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
hws[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_hw_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
|
||||
hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
|
||||
|
||||
hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE];
|
||||
hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE];
|
||||
hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE];
|
||||
hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER];
|
||||
hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER];
|
||||
hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER];
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MN_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels));
|
||||
|
||||
/* BUS */
|
||||
hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
|
||||
|
@ -523,12 +530,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
hws[IMX8MN_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
|
||||
hws[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
|
||||
hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0);
|
||||
hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk", "gpu_core", base + 0x44f0, 0);
|
||||
hws[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
|
||||
hws[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
|
||||
hws[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
|
||||
|
@ -551,11 +559,14 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MN_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MN_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MN_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MN_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MN_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MN_SYS_PLL1_800M]->clk);
|
||||
hws[IMX8MN_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MN_CLK_A53_SRC], hws[IMX8MN_SYS_PLL1_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MN_CLK_A53_CORE], hws[IMX8MN_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MN_CLK_END);
|
||||
|
||||
|
|
|
@ -4,13 +4,13 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mp-clock.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
@ -34,6 +34,8 @@ static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
|
|||
"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
|
||||
"audio_pll1_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m",
|
||||
"vpu_pll_out", "sys_pll1_800m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll3_out", };
|
||||
|
@ -342,7 +344,7 @@ static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_26
|
|||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mp_hdmi_27m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
static const char * const imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
|
@ -434,6 +436,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!anatop_base))
|
||||
return -ENOMEM;
|
||||
|
||||
|
@ -553,6 +556,9 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
|
||||
hws[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0, 3);
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MP_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels));
|
||||
|
||||
hws[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800);
|
||||
hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880);
|
||||
hws[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900);
|
||||
|
@ -631,7 +637,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00);
|
||||
hws[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80);
|
||||
hws[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00);
|
||||
hws[IMX8MP_CLK_HDMI_27M] = imx8m_clk_hw_composite("hdmi_27m", imx8mp_hdmi_27m_sels, ccm_base + 0xbb80);
|
||||
hws[IMX8MP_CLK_HDMI_24M] = imx8m_clk_hw_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm_base + 0xbb80);
|
||||
hws[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00);
|
||||
hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
|
||||
hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
|
||||
|
@ -671,6 +677,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
|
||||
hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
|
||||
hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
|
||||
hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
|
||||
hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
|
||||
hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
|
||||
hws[IMX8MP_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0);
|
||||
|
@ -722,11 +729,14 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
|
||||
hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0);
|
||||
|
||||
hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MP_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MP_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MP_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MP_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MP_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MP_SYS_PLL1_800M]->clk);
|
||||
hws[IMX8MP_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC], hws[IMX8MP_SYS_PLL1_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE], hws[IMX8MP_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MP_CLK_END);
|
||||
|
||||
|
|
|
@ -5,7 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
|
@ -41,6 +41,8 @@ static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
|
|||
static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
|
||||
|
||||
|
@ -305,6 +307,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base))
|
||||
return -ENOMEM;
|
||||
|
||||
|
@ -403,22 +406,29 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
/* CORE */
|
||||
hws[IMX8MQ_CLK_A53_SRC] = imx_clk_hw_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));
|
||||
hws[IMX8MQ_CLK_M4_SRC] = imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels));
|
||||
hws[IMX8MQ_CLK_VPU_SRC] = imx_clk_hw_mux2("vpu_src", base + 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));
|
||||
hws[IMX8MQ_CLK_GPU_CORE_SRC] = imx_clk_hw_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_SRC] = imx_clk_hw_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mq_gpu_shader_sels, ARRAY_SIZE(imx8mq_gpu_shader_sels));
|
||||
|
||||
hws[IMX8MQ_CLK_A53_CG] = imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);
|
||||
hws[IMX8MQ_CLK_M4_CG] = imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
|
||||
hws[IMX8MQ_CLK_VPU_CG] = imx_clk_hw_gate3("vpu_cg", "vpu_src", base + 0x8100, 28);
|
||||
hws[IMX8MQ_CLK_GPU_CORE_CG] = imx_clk_hw_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28);
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_CG] = imx_clk_hw_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);
|
||||
|
||||
hws[IMX8MQ_CLK_A53_DIV] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);
|
||||
hws[IMX8MQ_CLK_M4_DIV] = imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
|
||||
hws[IMX8MQ_CLK_VPU_DIV] = imx_clk_hw_divider2("vpu_div", "vpu_cg", base + 0x8100, 0, 3);
|
||||
hws[IMX8MQ_CLK_GPU_CORE_DIV] = imx_clk_hw_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_DIV] = imx_clk_hw_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3);
|
||||
|
||||
hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core", imx8mq_arm_m4_sels, base + 0x8080);
|
||||
hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core", imx8mq_vpu_sels, base + 0x8100);
|
||||
hws[IMX8MQ_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mq_gpu_core_sels, base + 0x8180);
|
||||
hws[IMX8MQ_CLK_GPU_SHADER] = imx8m_clk_hw_composite("gpu_shader", imx8mq_gpu_shader_sels, base + 0x8200);
|
||||
/* For backwards compatibility */
|
||||
hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE];
|
||||
hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE];
|
||||
hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE];
|
||||
hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE];
|
||||
hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE];
|
||||
hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_CORE_CG] = hws[IMX8MQ_CLK_GPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_CORE_DIV] = hws[IMX8MQ_CLK_GPU_CORE];
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_SRC] = hws[IMX8MQ_CLK_GPU_SHADER];
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_CG] = hws[IMX8MQ_CLK_GPU_SHADER];
|
||||
hws[IMX8MQ_CLK_GPU_SHADER_DIV] = hws[IMX8MQ_CLK_GPU_SHADER];
|
||||
|
||||
/* CORE SEL */
|
||||
hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels));
|
||||
|
||||
/* BUS */
|
||||
hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
|
||||
|
@ -567,7 +577,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
|
||||
hws[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
|
||||
hws[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_hw_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
hws[IMX8MQ_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0);
|
||||
hws[IMX8MQ_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_core", base + 0x4570, 0);
|
||||
hws[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_hw_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
hws[IMX8MQ_CLK_DISP_ROOT] = imx_clk_hw_gate2_shared2("disp_root_clk", "disp_dc8000", base + 0x45d0, 0, &share_count_dcss);
|
||||
hws[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_dcss);
|
||||
|
@ -583,11 +593,14 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc_25m", 1, 8);
|
||||
hws[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
|
||||
hws[IMX8MQ_CLK_A53_DIV]->clk,
|
||||
hws[IMX8MQ_CLK_A53_SRC]->clk,
|
||||
hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MQ_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MQ_CLK_A53_CORE]->clk,
|
||||
hws[IMX8MQ_ARM_PLL_OUT]->clk,
|
||||
hws[IMX8MQ_SYS1_PLL_800M]->clk);
|
||||
hws[IMX8MQ_CLK_A53_DIV]->clk);
|
||||
|
||||
clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC], hws[IMX8MQ_SYS1_PLL_800M]);
|
||||
clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE], hws[IMX8MQ_ARM_PLL_OUT]);
|
||||
|
||||
imx_check_clk_hws(hws, IMX8MQ_CLK_END);
|
||||
|
||||
|
|
|
@ -98,26 +98,45 @@ static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
|
|||
return tmp;
|
||||
}
|
||||
|
||||
static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
static int clk_pfdv2_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
u64 tmp = *prate;
|
||||
unsigned long parent_rates[] = {
|
||||
480000000,
|
||||
528000000,
|
||||
req->best_parent_rate
|
||||
};
|
||||
unsigned long best_rate = -1UL, rate = req->rate;
|
||||
unsigned long best_parent_rate = req->best_parent_rate;
|
||||
u64 tmp;
|
||||
u8 frac;
|
||||
int i;
|
||||
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
for (i = 0; i < ARRAY_SIZE(parent_rates); i++) {
|
||||
tmp = parent_rates[i];
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
|
||||
if (frac < 12)
|
||||
frac = 12;
|
||||
else if (frac > 35)
|
||||
frac = 35;
|
||||
if (frac < 12)
|
||||
frac = 12;
|
||||
else if (frac > 35)
|
||||
frac = 35;
|
||||
|
||||
tmp = *prate;
|
||||
tmp *= 18;
|
||||
do_div(tmp, frac);
|
||||
tmp = parent_rates[i];
|
||||
tmp *= 18;
|
||||
do_div(tmp, frac);
|
||||
|
||||
return tmp;
|
||||
if (abs(tmp - req->rate) < abs(best_rate - req->rate)) {
|
||||
best_rate = tmp;
|
||||
best_parent_rate = parent_rates[i];
|
||||
}
|
||||
}
|
||||
|
||||
req->best_parent_rate = best_parent_rate;
|
||||
req->rate = best_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pfdv2_is_enabled(struct clk_hw *hw)
|
||||
|
@ -139,6 +158,12 @@ static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
u32 val;
|
||||
u8 frac;
|
||||
|
||||
if (!rate)
|
||||
return -EINVAL;
|
||||
|
||||
/* PFD can NOT change rate without gating */
|
||||
WARN_ON(clk_pfdv2_is_enabled(hw));
|
||||
|
||||
tmp = tmp * 18 + rate / 2;
|
||||
do_div(tmp, rate);
|
||||
frac = tmp;
|
||||
|
@ -161,7 +186,7 @@ static const struct clk_ops clk_pfdv2_ops = {
|
|||
.enable = clk_pfdv2_enable,
|
||||
.disable = clk_pfdv2_disable,
|
||||
.recalc_rate = clk_pfdv2_recalc_rate,
|
||||
.round_rate = clk_pfdv2_round_rate,
|
||||
.determine_rate = clk_pfdv2_determine_rate,
|
||||
.set_rate = clk_pfdv2_set_rate,
|
||||
.is_enabled = clk_pfdv2_is_enabled,
|
||||
};
|
||||
|
@ -189,7 +214,7 @@ struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
|
|||
init.ops = &clk_pfdv2_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_SET_RATE_GATE;
|
||||
init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
|
||||
|
||||
pfd->hw.init = &init;
|
||||
|
||||
|
|
|
@ -55,8 +55,10 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
|
|||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
|
||||
PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
@ -408,6 +410,8 @@ struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
|
|||
default:
|
||||
pr_err("%s: Unknown pll type for pll clk %s\n",
|
||||
__func__, name);
|
||||
kfree(pll);
|
||||
return ERR_PTR(-EINVAL);
|
||||
};
|
||||
|
||||
pll->base = base;
|
||||
|
|
|
@ -54,7 +54,7 @@ static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
|
|||
csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
|
||||
}
|
||||
|
||||
static int clk_pllv4_is_enabled(struct clk_hw *hw)
|
||||
static int clk_pllv4_is_prepared(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
|
||||
|
@ -175,7 +175,7 @@ static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pllv4_enable(struct clk_hw *hw)
|
||||
static int clk_pllv4_prepare(struct clk_hw *hw)
|
||||
{
|
||||
u32 val;
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
|
@ -187,7 +187,7 @@ static int clk_pllv4_enable(struct clk_hw *hw)
|
|||
return clk_pllv4_wait_lock(pll);
|
||||
}
|
||||
|
||||
static void clk_pllv4_disable(struct clk_hw *hw)
|
||||
static void clk_pllv4_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
u32 val;
|
||||
struct clk_pllv4 *pll = to_clk_pllv4(hw);
|
||||
|
@ -201,9 +201,9 @@ static const struct clk_ops clk_pllv4_ops = {
|
|||
.recalc_rate = clk_pllv4_recalc_rate,
|
||||
.round_rate = clk_pllv4_round_rate,
|
||||
.set_rate = clk_pllv4_set_rate,
|
||||
.enable = clk_pllv4_enable,
|
||||
.disable = clk_pllv4_disable,
|
||||
.is_enabled = clk_pllv4_is_enabled,
|
||||
.prepare = clk_pllv4_prepare,
|
||||
.unprepare = clk_pllv4_unprepare,
|
||||
.is_prepared = clk_pllv4_is_prepared,
|
||||
};
|
||||
|
||||
struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
|
||||
|
|
|
@ -195,10 +195,10 @@ static int clk_sscg_pll2_find_setup(struct clk_sscg_pll_setup *setup,
|
|||
uint64_t ref)
|
||||
{
|
||||
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
if (ref < PLL_STAGE1_MIN_FREQ || ref > PLL_STAGE1_MAX_FREQ)
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
|
||||
temp_setup->vco1 = ref;
|
||||
|
||||
|
@ -254,10 +254,10 @@ static int clk_sscg_pll1_find_setup(struct clk_sscg_pll_setup *setup,
|
|||
uint64_t ref)
|
||||
{
|
||||
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
if (ref < PLL_REF_MIN_FREQ || ref > PLL_REF_MAX_FREQ)
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
|
||||
temp_setup->ref = ref;
|
||||
|
||||
|
@ -428,7 +428,7 @@ static int __clk_sscg_pll_determine_rate(struct clk_hw *hw,
|
|||
struct clk_sscg_pll_setup *setup = &pll->setup;
|
||||
struct clk_hw *parent_hw = NULL;
|
||||
int bypass_parent_index;
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
req->max_rate = max;
|
||||
req->min_rate = min;
|
||||
|
@ -467,10 +467,10 @@ static int clk_sscg_pll_determine_rate(struct clk_hw *hw,
|
|||
uint64_t rate = req->rate;
|
||||
uint64_t min = req->min_rate;
|
||||
uint64_t max = req->max_rate;
|
||||
int ret = -EINVAL;
|
||||
int ret;
|
||||
|
||||
if (rate < PLL_OUT_MIN_FREQ || rate > PLL_OUT_MAX_FREQ)
|
||||
return ret;
|
||||
return -EINVAL;
|
||||
|
||||
ret = __clk_sscg_pll_determine_rate(hw, req, req->rate, req->rate,
|
||||
rate, PLL_BYPASS2);
|
||||
|
|
|
@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
|
|||
struct clk *div, struct clk *mux, struct clk *pll,
|
||||
struct clk *step);
|
||||
|
||||
#define IMX_COMPOSITE_CORE BIT(0)
|
||||
|
||||
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
||||
const char * const *parent_names,
|
||||
int num_parents,
|
||||
void __iomem *reg,
|
||||
u32 composite_flags,
|
||||
unsigned long flags);
|
||||
|
||||
#define imx8m_clk_hw_composite_core(name, parent_names, reg) \
|
||||
imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||
ARRAY_SIZE(parent_names), reg, \
|
||||
IMX_COMPOSITE_CORE, \
|
||||
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
||||
|
||||
#define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
|
||||
flags) \
|
||||
to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||
num_parents, reg, flags))
|
||||
num_parents, reg, 0, flags))
|
||||
|
||||
#define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
|
||||
imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||
ARRAY_SIZE(parent_names), reg, \
|
||||
ARRAY_SIZE(parent_names), reg, 0, \
|
||||
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
||||
|
||||
#define __imx8m_clk_composite(name, parent_names, reg, flags) \
|
||||
|
|
|
@ -280,6 +280,15 @@ config SC_GPUCC_7180
|
|||
Say Y if you want to support graphics controller devices and
|
||||
functionality such as 3D graphics.
|
||||
|
||||
config SC_MSS_7180
|
||||
tristate "SC7180 Modem Clock Controller"
|
||||
select SC_GCC_7180
|
||||
help
|
||||
Support for the Modem Subsystem clock controller on Qualcomm
|
||||
Technologies, Inc on SC7180 devices.
|
||||
Say Y if you want to use the Modem branch clocks of the Modem
|
||||
subsystem clock controller to reset the MSS subsystem.
|
||||
|
||||
config SC_VIDEOCC_7180
|
||||
tristate "SC7180 Video Clock Controller"
|
||||
select SC_GCC_7180
|
||||
|
@ -366,6 +375,13 @@ config SM_GCC_8150
|
|||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SM_GCC_8250
|
||||
tristate "SM8250 Global Clock Controller"
|
||||
help
|
||||
Support for the global clock controller on SM8250 devices.
|
||||
Say Y if you want to use peripheral devices such as UART,
|
||||
SPI, I2C, USB, SD/UFS, PCIe etc.
|
||||
|
||||
config SPMI_PMIC_CLKDIV
|
||||
tristate "SPMI PMIC clkdiv Support"
|
||||
depends on SPMI || COMPILE_TEST
|
||||
|
|
|
@ -50,6 +50,7 @@ obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
|
|||
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
|
||||
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
|
||||
obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
|
||||
obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o
|
||||
obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o
|
||||
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
|
||||
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
|
||||
|
@ -59,6 +60,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
|
|||
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
|
||||
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
|
||||
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
|
||||
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
|
||||
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
|
||||
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
|
||||
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
|
||||
|
|
|
@ -52,6 +52,7 @@
|
|||
#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
|
||||
#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
|
||||
#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
|
||||
#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
|
||||
#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
|
||||
#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
|
||||
#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
|
||||
|
@ -116,6 +117,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
|
|||
[PLL_OFF_ALPHA_VAL] = 0x40,
|
||||
[PLL_OFF_CAL_VAL] = 0x44,
|
||||
},
|
||||
[CLK_ALPHA_PLL_TYPE_LUCID] = {
|
||||
[PLL_OFF_L_VAL] = 0x04,
|
||||
[PLL_OFF_CAL_L_VAL] = 0x08,
|
||||
[PLL_OFF_USER_CTL] = 0x0c,
|
||||
[PLL_OFF_USER_CTL_U] = 0x10,
|
||||
[PLL_OFF_USER_CTL_U1] = 0x14,
|
||||
[PLL_OFF_CONFIG_CTL] = 0x18,
|
||||
[PLL_OFF_CONFIG_CTL_U] = 0x1c,
|
||||
[PLL_OFF_CONFIG_CTL_U1] = 0x20,
|
||||
[PLL_OFF_TEST_CTL] = 0x24,
|
||||
[PLL_OFF_TEST_CTL_U] = 0x28,
|
||||
[PLL_OFF_TEST_CTL_U1] = 0x2c,
|
||||
[PLL_OFF_STATUS] = 0x30,
|
||||
[PLL_OFF_OPMODE] = 0x38,
|
||||
[PLL_OFF_ALPHA_VAL] = 0x40,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
||||
|
||||
|
@ -134,15 +151,14 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
|
|||
#define PLL_HUAYRA_N_MASK 0xff
|
||||
#define PLL_HUAYRA_ALPHA_WIDTH 16
|
||||
|
||||
#define FABIA_OPMODE_STANDBY 0x0
|
||||
#define FABIA_OPMODE_RUN 0x1
|
||||
#define PLL_STANDBY 0x0
|
||||
#define PLL_RUN 0x1
|
||||
#define PLL_OUT_MASK 0x7
|
||||
#define PLL_RATE_MARGIN 500
|
||||
|
||||
#define FABIA_PLL_OUT_MASK 0x7
|
||||
#define FABIA_PLL_RATE_MARGIN 500
|
||||
|
||||
#define TRION_PLL_STANDBY 0x0
|
||||
#define TRION_PLL_RUN 0x1
|
||||
#define TRION_PLL_OUT_MASK 0x7
|
||||
/* LUCID PLL specific settings and offsets */
|
||||
#define LUCID_PLL_CAL_VAL 0x44
|
||||
#define LUCID_PCAL_DONE BIT(26)
|
||||
|
||||
#define pll_alpha_width(p) \
|
||||
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
|
||||
|
@ -544,7 +560,8 @@ static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
|
||||
vco = alpha_pll_find_vco(pll, rate);
|
||||
if (pll->vco_table && !vco) {
|
||||
pr_err("alpha pll not in a valid vco range\n");
|
||||
pr_err("%s: alpha pll not in a valid vco range\n",
|
||||
clk_hw_get_name(hw));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -722,7 +739,7 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
*/
|
||||
if (clk_alpha_pll_is_enabled(hw)) {
|
||||
if (cur_alpha != a) {
|
||||
pr_err("clock needs to be gated %s\n",
|
||||
pr_err("%s: clock needs to be gated\n",
|
||||
clk_hw_get_name(hw));
|
||||
return -EBUSY;
|
||||
}
|
||||
|
@ -765,7 +782,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
|
|||
if (ret)
|
||||
return 0;
|
||||
|
||||
return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
|
||||
return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
|
||||
}
|
||||
|
||||
static int clk_trion_pll_is_enabled(struct clk_hw *hw)
|
||||
|
@ -795,7 +812,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
|
|||
}
|
||||
|
||||
/* Set operation mode to RUN */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
|
||||
|
||||
ret = wait_for_pll_enable_lock(pll);
|
||||
if (ret)
|
||||
|
@ -803,7 +820,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
|
|||
|
||||
/* Enable the PLL outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
|
||||
TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
|
||||
PLL_OUT_MASK, PLL_OUT_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -836,12 +853,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
|
|||
|
||||
/* Disable the PLL outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
|
||||
TRION_PLL_OUT_MASK, 0);
|
||||
PLL_OUT_MASK, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Place the PLL mode in STANDBY */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
}
|
||||
|
||||
|
@ -849,33 +866,12 @@ static unsigned long
|
|||
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
struct regmap *regmap = pll->clkr.regmap;
|
||||
u32 l, frac;
|
||||
u64 prate = parent_rate;
|
||||
u32 l, frac, alpha_width = pll_alpha_width(pll);
|
||||
|
||||
regmap_read(regmap, PLL_L_VAL(pll), &l);
|
||||
regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
|
||||
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
|
||||
regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
|
||||
|
||||
return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
|
||||
}
|
||||
|
||||
static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
unsigned long min_freq, max_freq;
|
||||
u32 l;
|
||||
u64 a;
|
||||
|
||||
rate = alpha_pll_round_rate(rate, *prate,
|
||||
&l, &a, ALPHA_REG_16BIT_WIDTH);
|
||||
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
|
||||
return rate;
|
||||
|
||||
min_freq = pll->vco_table[0].min_freq;
|
||||
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
|
||||
|
||||
return clamp(rate, min_freq, max_freq);
|
||||
return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fixed_ops = {
|
||||
|
@ -921,7 +917,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
|
|||
.disable = clk_trion_pll_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = clk_trion_pll_recalc_rate,
|
||||
.round_rate = clk_trion_pll_round_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
|
||||
|
||||
|
@ -1088,14 +1084,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
|
|||
return ret;
|
||||
|
||||
/* Skip If PLL is already running */
|
||||
if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
|
||||
if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
|
||||
return 0;
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
|
||||
ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -1104,7 +1100,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
|
||||
ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -1113,7 +1109,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
|
|||
return ret;
|
||||
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
|
||||
FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
|
||||
PLL_OUT_MASK, PLL_OUT_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -1143,13 +1139,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
|
|||
return;
|
||||
|
||||
/* Disable main outputs */
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
|
||||
0);
|
||||
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
/* Place the PLL in STANDBY */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
}
|
||||
|
||||
static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
|
||||
|
@ -1170,7 +1165,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 l, alpha_width = pll_alpha_width(pll);
|
||||
u64 a;
|
||||
unsigned long rrate;
|
||||
unsigned long rrate, max = rate + PLL_RATE_MARGIN;
|
||||
|
||||
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
|
||||
|
||||
|
@ -1178,8 +1173,9 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
* Due to limited number of bits for fractional rate programming, the
|
||||
* rounded up rate could be marginally higher than the requested rate.
|
||||
*/
|
||||
if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
|
||||
pr_err("Call set rate on the PLL with rounded rates!\n");
|
||||
if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
|
||||
pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
|
||||
clk_hw_get_name(hw), rrate, rate, max);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -1196,6 +1192,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
|
|||
struct clk_hw *parent_hw;
|
||||
unsigned long cal_freq, rrate;
|
||||
u32 cal_l, val, alpha_width = pll_alpha_width(pll);
|
||||
const char *name = clk_hw_get_name(hw);
|
||||
u64 a;
|
||||
int ret;
|
||||
|
||||
|
@ -1210,7 +1207,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
|
|||
|
||||
vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
|
||||
if (!vco) {
|
||||
pr_err("alpha pll: not in a valid vco range\n");
|
||||
pr_err("%s: alpha pll not in a valid vco range\n", name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
@ -1227,7 +1224,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
|
|||
* Due to a limited number of bits for fractional rate programming, the
|
||||
* rounded up rate could be marginally higher than the requested rate.
|
||||
*/
|
||||
if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
|
||||
if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
|
||||
return -EINVAL;
|
||||
|
||||
/* Setup PLL for calibration frequency */
|
||||
|
@ -1236,7 +1233,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
|
|||
/* Bringup the PLL at calibration frequency */
|
||||
ret = clk_alpha_pll_enable(hw);
|
||||
if (ret) {
|
||||
pr_err("alpha pll calibration failed\n");
|
||||
pr_err("%s: alpha pll calibration failed\n", name);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -1394,3 +1391,175 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
|
|||
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
|
||||
|
||||
/**
|
||||
* clk_lucid_pll_configure - configure the lucid pll
|
||||
*
|
||||
* @pll: clk alpha pll
|
||||
* @regmap: register map
|
||||
* @config: configuration to apply for pll
|
||||
*/
|
||||
void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config)
|
||||
{
|
||||
if (config->l)
|
||||
regmap_write(regmap, PLL_L_VAL(pll), config->l);
|
||||
|
||||
regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
|
||||
|
||||
if (config->alpha)
|
||||
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
|
||||
|
||||
if (config->config_ctl_val)
|
||||
regmap_write(regmap, PLL_CONFIG_CTL(pll),
|
||||
config->config_ctl_val);
|
||||
|
||||
if (config->config_ctl_hi_val)
|
||||
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
|
||||
config->config_ctl_hi_val);
|
||||
|
||||
if (config->config_ctl_hi1_val)
|
||||
regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
|
||||
config->config_ctl_hi1_val);
|
||||
|
||||
if (config->user_ctl_val)
|
||||
regmap_write(regmap, PLL_USER_CTL(pll),
|
||||
config->user_ctl_val);
|
||||
|
||||
if (config->user_ctl_hi_val)
|
||||
regmap_write(regmap, PLL_USER_CTL_U(pll),
|
||||
config->user_ctl_hi_val);
|
||||
|
||||
if (config->user_ctl_hi1_val)
|
||||
regmap_write(regmap, PLL_USER_CTL_U1(pll),
|
||||
config->user_ctl_hi1_val);
|
||||
|
||||
if (config->test_ctl_val)
|
||||
regmap_write(regmap, PLL_TEST_CTL(pll),
|
||||
config->test_ctl_val);
|
||||
|
||||
if (config->test_ctl_hi_val)
|
||||
regmap_write(regmap, PLL_TEST_CTL_U(pll),
|
||||
config->test_ctl_hi_val);
|
||||
|
||||
if (config->test_ctl_hi1_val)
|
||||
regmap_write(regmap, PLL_TEST_CTL_U1(pll),
|
||||
config->test_ctl_hi1_val);
|
||||
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
|
||||
PLL_UPDATE_BYPASS);
|
||||
|
||||
/* Disable PLL output */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
|
||||
|
||||
/* Set operation mode to OFF */
|
||||
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
|
||||
|
||||
/* Place the PLL in STANDBY mode */
|
||||
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
|
||||
|
||||
/*
|
||||
* The Lucid PLL requires a power-on self-calibration which happens when the
|
||||
* PLL comes out of reset. Calibrate in case it is not completed.
|
||||
*/
|
||||
static int alpha_pll_lucid_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
u32 regval;
|
||||
int ret;
|
||||
|
||||
/* Return early if calibration is not needed. */
|
||||
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), ®val);
|
||||
if (regval & LUCID_PCAL_DONE)
|
||||
return 0;
|
||||
|
||||
/* On/off to calibrate */
|
||||
ret = clk_trion_pll_enable(hw);
|
||||
if (!ret)
|
||||
clk_trion_pll_disable(hw);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate)
|
||||
{
|
||||
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
|
||||
unsigned long rrate;
|
||||
u32 regval, l, alpha_width = pll_alpha_width(pll);
|
||||
u64 a;
|
||||
int ret;
|
||||
|
||||
rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
|
||||
|
||||
/*
|
||||
* Due to a limited number of bits for fractional rate programming, the
|
||||
* rounded up rate could be marginally higher than the requested rate.
|
||||
*/
|
||||
if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
|
||||
pr_err("Call set rate on the PLL with rounded rates!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
|
||||
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
|
||||
|
||||
/* Latch the PLL input */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
PLL_UPDATE, PLL_UPDATE);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Wait for 2 reference cycles before checking the ACK bit. */
|
||||
udelay(1);
|
||||
regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val);
|
||||
if (!(regval & ALPHA_PLL_ACK_LATCH)) {
|
||||
pr_err("Lucid PLL latch failed. Output may be unstable!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Return the latch input to 0 */
|
||||
ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
|
||||
PLL_UPDATE, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (clk_hw_is_enabled(hw)) {
|
||||
ret = wait_for_pll_enable_lock(pll);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Wait for PLL output to stabilize */
|
||||
udelay(100);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_lucid_ops = {
|
||||
.prepare = alpha_pll_lucid_prepare,
|
||||
.enable = clk_trion_pll_enable,
|
||||
.disable = clk_trion_pll_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = clk_trion_pll_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
.set_rate = alpha_pll_lucid_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
|
||||
.enable = clk_trion_pll_enable,
|
||||
.disable = clk_trion_pll_disable,
|
||||
.is_enabled = clk_trion_pll_is_enabled,
|
||||
.recalc_rate = clk_trion_pll_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
|
||||
|
||||
const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
|
||||
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
|
||||
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
|
||||
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
|
||||
|
|
|
@ -14,6 +14,7 @@ enum {
|
|||
CLK_ALPHA_PLL_TYPE_BRAMMO,
|
||||
CLK_ALPHA_PLL_TYPE_FABIA,
|
||||
CLK_ALPHA_PLL_TYPE_TRION,
|
||||
CLK_ALPHA_PLL_TYPE_LUCID,
|
||||
CLK_ALPHA_PLL_TYPE_MAX,
|
||||
};
|
||||
|
||||
|
@ -30,6 +31,7 @@ enum {
|
|||
PLL_OFF_CONFIG_CTL_U1,
|
||||
PLL_OFF_TEST_CTL,
|
||||
PLL_OFF_TEST_CTL_U,
|
||||
PLL_OFF_TEST_CTL_U1,
|
||||
PLL_OFF_STATUS,
|
||||
PLL_OFF_OPMODE,
|
||||
PLL_OFF_FRAC,
|
||||
|
@ -94,10 +96,13 @@ struct alpha_pll_config {
|
|||
u32 alpha_hi;
|
||||
u32 config_ctl_val;
|
||||
u32 config_ctl_hi_val;
|
||||
u32 config_ctl_hi1_val;
|
||||
u32 user_ctl_val;
|
||||
u32 user_ctl_hi_val;
|
||||
u32 user_ctl_hi1_val;
|
||||
u32 test_ctl_val;
|
||||
u32 test_ctl_hi_val;
|
||||
u32 test_ctl_hi1_val;
|
||||
u32 main_output_mask;
|
||||
u32 aux_output_mask;
|
||||
u32 aux2_output_mask;
|
||||
|
@ -123,10 +128,17 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
|
|||
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_lucid_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
|
||||
|
||||
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
|
||||
const struct alpha_pll_config *config);
|
||||
|
||||
extern const struct clk_ops clk_trion_fixed_pll_ops;
|
||||
extern const struct clk_ops clk_trion_pll_postdiv_ops;
|
||||
|
||||
|
|
|
@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk_apq8064 = {
|
|||
.num_clks = ARRAY_SIZE(apq8064_clks),
|
||||
};
|
||||
|
||||
/* ipq806x */
|
||||
DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
|
||||
DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
|
||||
|
||||
static struct clk_rpm *ipq806x_clks[] = {
|
||||
[RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
|
||||
[RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
|
||||
[RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
|
||||
[RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
|
||||
[RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
|
||||
[RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
|
||||
[RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
|
||||
[RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
|
||||
[RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
|
||||
[RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
|
||||
[RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
|
||||
[RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
|
||||
[RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
|
||||
[RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
|
||||
[RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
|
||||
[RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
|
||||
};
|
||||
|
||||
static const struct rpm_clk_desc rpm_clk_ipq806x = {
|
||||
.clks = ipq806x_clks,
|
||||
.num_clks = ARRAY_SIZE(ipq806x_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id rpm_clk_match_table[] = {
|
||||
{ .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
|
||||
{ .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
|
||||
{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
|
||||
{ .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
|
@ -143,12 +143,22 @@ static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
|
|||
!= (c->aggr_state & BIT(state));
|
||||
}
|
||||
|
||||
static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state,
|
||||
struct tcs_cmd *cmd, bool wait)
|
||||
{
|
||||
if (wait)
|
||||
return rpmh_write(c->dev, state, cmd, 1);
|
||||
|
||||
return rpmh_write_async(c->dev, state, cmd, 1);
|
||||
}
|
||||
|
||||
static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
|
||||
{
|
||||
struct tcs_cmd cmd = { 0 };
|
||||
u32 cmd_state, on_val;
|
||||
enum rpmh_state state = RPMH_SLEEP_STATE;
|
||||
int ret;
|
||||
bool wait;
|
||||
|
||||
cmd.addr = c->res_addr;
|
||||
cmd_state = c->aggr_state;
|
||||
|
@ -159,7 +169,8 @@ static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
|
|||
if (cmd_state & BIT(state))
|
||||
cmd.data = on_val;
|
||||
|
||||
ret = rpmh_write_async(c->dev, state, &cmd, 1);
|
||||
wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE;
|
||||
ret = clk_rpmh_send(c, state, &cmd, wait);
|
||||
if (ret) {
|
||||
dev_err(c->dev, "set %s state of %s failed: (%d)\n",
|
||||
!state ? "sleep" :
|
||||
|
@ -216,7 +227,7 @@ static int clk_rpmh_prepare(struct clk_hw *hw)
|
|||
mutex_unlock(&rpmh_clk_lock);
|
||||
|
||||
return ret;
|
||||
};
|
||||
}
|
||||
|
||||
static void clk_rpmh_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
|
@ -248,38 +259,33 @@ static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
|
|||
{
|
||||
struct tcs_cmd cmd = { 0 };
|
||||
u32 cmd_state;
|
||||
int ret;
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&rpmh_clk_lock);
|
||||
|
||||
cmd_state = 0;
|
||||
if (enable) {
|
||||
cmd_state = 1;
|
||||
if (c->aggr_state)
|
||||
cmd_state = c->aggr_state;
|
||||
} else {
|
||||
cmd_state = 0;
|
||||
}
|
||||
|
||||
if (c->last_sent_aggr_state == cmd_state) {
|
||||
mutex_unlock(&rpmh_clk_lock);
|
||||
return 0;
|
||||
if (c->last_sent_aggr_state != cmd_state) {
|
||||
cmd.addr = c->res_addr;
|
||||
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
|
||||
|
||||
ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
|
||||
if (ret) {
|
||||
dev_err(c->dev, "set active state of %s failed: (%d)\n",
|
||||
c->res_name, ret);
|
||||
} else {
|
||||
c->last_sent_aggr_state = cmd_state;
|
||||
}
|
||||
}
|
||||
|
||||
cmd.addr = c->res_addr;
|
||||
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
|
||||
|
||||
ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
|
||||
if (ret) {
|
||||
dev_err(c->dev, "set active state of %s failed: (%d)\n",
|
||||
c->res_name, ret);
|
||||
mutex_unlock(&rpmh_clk_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
c->last_sent_aggr_state = cmd_state;
|
||||
|
||||
mutex_unlock(&rpmh_clk_lock);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
|
||||
|
@ -287,14 +293,14 @@ static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
|
|||
struct clk_rpmh *c = to_clk_rpmh(hw);
|
||||
|
||||
return clk_rpmh_bcm_send_cmd(c, true);
|
||||
};
|
||||
}
|
||||
|
||||
static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rpmh *c = to_clk_rpmh(hw);
|
||||
|
||||
clk_rpmh_bcm_send_cmd(c, false);
|
||||
};
|
||||
}
|
||||
|
||||
static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
|
@ -310,7 +316,7 @@ static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
clk_rpmh_bcm_send_cmd(c, true);
|
||||
|
||||
return 0;
|
||||
};
|
||||
}
|
||||
|
||||
static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
|
@ -404,6 +410,28 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
|
|||
.num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
|
||||
};
|
||||
|
||||
DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
|
||||
|
||||
static struct clk_hw *sm8250_rpmh_clocks[] = {
|
||||
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
|
||||
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
|
||||
[RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
|
||||
[RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
|
||||
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
|
||||
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
|
||||
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
|
||||
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
|
||||
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
|
||||
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
|
||||
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
|
||||
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
|
||||
};
|
||||
|
||||
static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
|
||||
.clks = sm8250_rpmh_clocks,
|
||||
.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
|
||||
};
|
||||
|
||||
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
|
@ -490,6 +518,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
|
|||
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
|
||||
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
|
||||
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
|
||||
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
|
||||
|
|
|
@ -525,6 +525,55 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
|
|||
.num_clks = ARRAY_SIZE(msm8974_clks),
|
||||
};
|
||||
|
||||
|
||||
/* msm8976 */
|
||||
DEFINE_CLK_SMD_RPM(msm8976, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(msm8976, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
|
||||
QCOM_SMD_RPM_BUS_CLK, 2);
|
||||
DEFINE_CLK_SMD_RPM(msm8976, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM_QDSS(msm8976, qdss_clk, qdss_a_clk,
|
||||
QCOM_SMD_RPM_MISC_CLK, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk1, bb_clk1_a, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk2, bb_clk2_a, 2);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, rf_clk2, rf_clk2_a, 5);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, div_clk2, div_clk2_a, 12);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk1_pin, bb_clk1_a_pin, 1);
|
||||
DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk2_pin, bb_clk2_a_pin, 2);
|
||||
|
||||
static struct clk_smd_rpm *msm8976_clks[] = {
|
||||
[RPM_SMD_PCNOC_CLK] = &msm8976_pcnoc_clk,
|
||||
[RPM_SMD_PCNOC_A_CLK] = &msm8976_pcnoc_a_clk,
|
||||
[RPM_SMD_SNOC_CLK] = &msm8976_snoc_clk,
|
||||
[RPM_SMD_SNOC_A_CLK] = &msm8976_snoc_a_clk,
|
||||
[RPM_SMD_BIMC_CLK] = &msm8976_bimc_clk,
|
||||
[RPM_SMD_BIMC_A_CLK] = &msm8976_bimc_a_clk,
|
||||
[RPM_SMD_QDSS_CLK] = &msm8976_qdss_clk,
|
||||
[RPM_SMD_QDSS_A_CLK] = &msm8976_qdss_a_clk,
|
||||
[RPM_SMD_BB_CLK1] = &msm8976_bb_clk1,
|
||||
[RPM_SMD_BB_CLK1_A] = &msm8976_bb_clk1_a,
|
||||
[RPM_SMD_BB_CLK2] = &msm8976_bb_clk2,
|
||||
[RPM_SMD_BB_CLK2_A] = &msm8976_bb_clk2_a,
|
||||
[RPM_SMD_RF_CLK2] = &msm8976_rf_clk2,
|
||||
[RPM_SMD_RF_CLK2_A] = &msm8976_rf_clk2_a,
|
||||
[RPM_SMD_BB_CLK1_PIN] = &msm8976_bb_clk1_pin,
|
||||
[RPM_SMD_BB_CLK1_A_PIN] = &msm8976_bb_clk1_a_pin,
|
||||
[RPM_SMD_BB_CLK2_PIN] = &msm8976_bb_clk2_pin,
|
||||
[RPM_SMD_BB_CLK2_A_PIN] = &msm8976_bb_clk2_a_pin,
|
||||
[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
|
||||
[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
|
||||
[RPM_SMD_DIV_CLK2] = &msm8976_div_clk2,
|
||||
[RPM_SMD_DIV_A_CLK2] = &msm8976_div_clk2_a,
|
||||
[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
|
||||
[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
|
||||
};
|
||||
|
||||
static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
|
||||
.clks = msm8976_clks,
|
||||
.num_clks = ARRAY_SIZE(msm8976_clks),
|
||||
};
|
||||
|
||||
/* msm8996 */
|
||||
DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
||||
DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
||||
|
@ -720,6 +769,7 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
|
|||
static const struct of_device_id rpm_smd_clk_match_table[] = {
|
||||
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
|
||||
{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
|
||||
{ .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
|
||||
{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
|
||||
{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
|
||||
{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
|
||||
|
|
|
@ -1224,6 +1224,8 @@ static struct clk_rcg prng_src = {
|
|||
.parent_map = gcc_pxo_pll8_map,
|
||||
},
|
||||
.clkr = {
|
||||
.enable_reg = 0x2e80,
|
||||
.enable_mask = BIT(11),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "prng_src",
|
||||
.parent_names = gcc_pxo_pll8,
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
|
@ -2165,6 +2165,71 @@ static struct clk_branch gcc_video_xo_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_mss_cfg_ahb_clk = {
|
||||
.halt_reg = 0x8a000,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8a000,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mss_cfg_ahb_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_mss_mfab_axis_clk = {
|
||||
.halt_reg = 0x8a004,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8a004,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mss_mfab_axis_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_mss_nav_axi_clk = {
|
||||
.halt_reg = 0x8a00c,
|
||||
.halt_check = BRANCH_HALT_VOTED,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8a00c,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mss_nav_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_mss_snoc_axi_clk = {
|
||||
.halt_reg = 0x8a150,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8a150,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mss_snoc_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
|
||||
.halt_reg = 0x8a154,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x8a154,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_mss_q6_memnoc_axi_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct gdsc ufs_phy_gdsc = {
|
||||
.gdscr = 0x77004,
|
||||
.pd = {
|
||||
|
@ -2336,6 +2401,11 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
|
|||
[GPLL7] = &gpll7.clkr,
|
||||
[GPLL4] = &gpll4.clkr,
|
||||
[GPLL1] = &gpll1.clkr,
|
||||
[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
|
||||
[GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
|
||||
[GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
|
||||
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
|
||||
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map gcc_sc7180_resets[] = {
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "reset.h"
|
||||
#include "gdsc.h"
|
||||
|
||||
enum {
|
||||
P_BI_TCXO,
|
||||
|
@ -3171,6 +3172,18 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0xf058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_prim_phy_pipe_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_usb3_sec_clkref_clk = {
|
||||
.halt_reg = 0x8c028,
|
||||
.halt_check = BRANCH_HALT,
|
||||
|
@ -3218,6 +3231,18 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
|
||||
.halt_check = BRANCH_HALT_SKIP,
|
||||
.clkr = {
|
||||
.enable_reg = 0x10058,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "gcc_usb3_sec_phy_pipe_clk",
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock ON depends on external parent 'config noc', so cant poll
|
||||
* delay and also mark as crtitical for video boot
|
||||
|
@ -3292,6 +3317,24 @@ static struct clk_branch gcc_video_xo_clk = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct gdsc usb30_prim_gdsc = {
|
||||
.gdscr = 0xf004,
|
||||
.pd = {
|
||||
.name = "usb30_prim_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct gdsc usb30_sec_gdsc = {
|
||||
.gdscr = 0x10004,
|
||||
.pd = {
|
||||
.name = "usb30_sec_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = POLL_CFG_GDSCR,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gcc_sm8150_clocks[] = {
|
||||
[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
|
||||
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
|
||||
|
@ -3480,10 +3523,12 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
|
|||
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
|
||||
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
|
||||
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
|
||||
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
|
||||
[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
|
||||
[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
|
||||
[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
|
||||
[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
|
||||
[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
|
||||
[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
|
||||
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
|
||||
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
|
||||
|
@ -3527,6 +3572,11 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = {
|
|||
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
|
||||
};
|
||||
|
||||
static struct gdsc *gcc_sm8150_gdscs[] = {
|
||||
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
|
||||
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
|
||||
};
|
||||
|
||||
static const struct regmap_config gcc_sm8150_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
|
@ -3541,6 +3591,8 @@ static const struct qcom_cc_desc gcc_sm8150_desc = {
|
|||
.num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
|
||||
.resets = gcc_sm8150_resets,
|
||||
.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
|
||||
.gdscs = gcc_sm8150_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
|
||||
};
|
||||
|
||||
static const struct of_device_id gcc_sm8150_match_table[] = {
|
||||
|
|
3690
drivers/clk/qcom/gcc-sm8250.c
Normal file
3690
drivers/clk/qcom/gcc-sm8250.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -170,8 +170,45 @@ static struct gdsc cx_gdsc = {
|
|||
.flags = VOTABLE,
|
||||
};
|
||||
|
||||
/*
|
||||
* On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU
|
||||
* running in the CX domain so the CPU doesn't need to know anything about the
|
||||
* GX domain EXCEPT....
|
||||
*
|
||||
* Hardware constraints dictate that the GX be powered down before the CX. If
|
||||
* the GMU crashes it could leave the GX on. In order to successfully bring back
|
||||
* the device the CPU needs to disable the GX headswitch. There being no sane
|
||||
* way to reach in and touch that register from deep inside the GPU driver we
|
||||
* need to set up the infrastructure to be able to ensure that the GPU can
|
||||
* ensure that the GX is off during this super special case. We do this by
|
||||
* defining a GX gdsc with a dummy enable function and a "default" disable
|
||||
* function.
|
||||
*
|
||||
* This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
|
||||
* driver. During power up, nothing will happen from the CPU (and the GMU will
|
||||
* power up normally but during power down this will ensure that the GX domain
|
||||
* is *really* off - this gives us a semi standard way of doing what we need.
|
||||
*/
|
||||
static int gx_gdsc_enable(struct generic_pm_domain *domain)
|
||||
{
|
||||
/* Do nothing but give genpd the impression that we were successful */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct gdsc gx_gdsc = {
|
||||
.gdscr = 0x100c,
|
||||
.clamp_io_ctrl = 0x1508,
|
||||
.pd = {
|
||||
.name = "gx_gdsc",
|
||||
.power_on = gx_gdsc_enable,
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = CLAMP_IO,
|
||||
};
|
||||
|
||||
static struct gdsc *gpu_cc_sc7180_gdscs[] = {
|
||||
[CX_GDSC] = &cx_gdsc,
|
||||
[GX_GDSC] = &gx_gdsc,
|
||||
};
|
||||
|
||||
static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
|
||||
|
|
143
drivers/clk/qcom/mss-sc7180.c
Normal file
143
drivers/clk/qcom/mss-sc7180.c
Normal file
|
@ -0,0 +1,143 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include <dt-bindings/clock/qcom,mss-sc7180.h>
|
||||
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-branch.h"
|
||||
#include "common.h"
|
||||
|
||||
static struct clk_branch mss_axi_nav_clk = {
|
||||
.halt_reg = 0x20bc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x20bc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mss_axi_nav_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "gcc_mss_nav_axi",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_branch mss_axi_crypto_clk = {
|
||||
.halt_reg = 0x20cc,
|
||||
.halt_check = BRANCH_HALT,
|
||||
.clkr = {
|
||||
.enable_reg = 0x20cc,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "mss_axi_crypto_clk",
|
||||
.parent_data = &(const struct clk_parent_data){
|
||||
.fw_name = "gcc_mss_mfab_axis",
|
||||
},
|
||||
.num_parents = 1,
|
||||
.ops = &clk_branch2_ops,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct regmap_config mss_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.fast_io = true,
|
||||
.max_register = 0x41aa0cc,
|
||||
};
|
||||
|
||||
static struct clk_regmap *mss_sc7180_clocks[] = {
|
||||
[MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
|
||||
[MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc mss_sc7180_desc = {
|
||||
.config = &mss_regmap_config,
|
||||
.clks = mss_sc7180_clocks,
|
||||
.num_clks = ARRAY_SIZE(mss_sc7180_clocks),
|
||||
};
|
||||
|
||||
static int mss_sc7180_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
ret = pm_clk_create(&pdev->dev);
|
||||
if (ret)
|
||||
goto disable_pm_runtime;
|
||||
|
||||
ret = pm_clk_add(&pdev->dev, "cfg_ahb");
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "failed to acquire iface clock\n");
|
||||
goto destroy_pm_clk;
|
||||
}
|
||||
|
||||
ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
|
||||
if (ret < 0)
|
||||
goto destroy_pm_clk;
|
||||
|
||||
return 0;
|
||||
|
||||
destroy_pm_clk:
|
||||
pm_clk_destroy(&pdev->dev);
|
||||
|
||||
disable_pm_runtime:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mss_sc7180_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_clk_destroy(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops mss_sc7180_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
|
||||
};
|
||||
|
||||
static const struct of_device_id mss_sc7180_match_table[] = {
|
||||
{ .compatible = "qcom,sc7180-mss" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mss_sc7180_match_table);
|
||||
|
||||
static struct platform_driver mss_sc7180_driver = {
|
||||
.probe = mss_sc7180_probe,
|
||||
.remove = mss_sc7180_remove,
|
||||
.driver = {
|
||||
.name = "sc7180-mss",
|
||||
.of_match_table = mss_sc7180_match_table,
|
||||
.pm = &mss_sc7180_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init mss_sc7180_init(void)
|
||||
{
|
||||
return platform_driver_register(&mss_sc7180_driver);
|
||||
}
|
||||
subsys_initcall(mss_sc7180_init);
|
||||
|
||||
static void __exit mss_sc7180_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&mss_sc7180_driver);
|
||||
}
|
||||
module_exit(mss_sc7180_exit);
|
||||
|
||||
MODULE_DESCRIPTION("QTI MSS SC7180 Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -13,4 +13,12 @@ config SPRD_SC9860_CLK
|
|||
tristate "Support for the Spreadtrum SC9860 clocks"
|
||||
depends on (ARM64 && ARCH_SPRD) || COMPILE_TEST
|
||||
default ARM64 && ARCH_SPRD
|
||||
|
||||
config SPRD_SC9863A_CLK
|
||||
tristate "Support for the Spreadtrum SC9863A clocks"
|
||||
depends on (ARM64 && ARCH_SPRD) || COMPILE_TEST
|
||||
default ARM64 && ARCH_SPRD
|
||||
help
|
||||
Support for the global clock controller on sc9863a devices.
|
||||
Say Y if you want to use peripheral devices on sc9863a SoC.
|
||||
endif
|
||||
|
|
|
@ -10,3 +10,4 @@ clk-sprd-y += pll.o
|
|||
|
||||
## SoC support
|
||||
obj-$(CONFIG_SPRD_SC9860_CLK) += sc9860-clk.o
|
||||
obj-$(CONFIG_SPRD_SC9863A_CLK) += sc9863a-clk.o
|
||||
|
|
|
@ -40,7 +40,8 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
|
|||
const struct sprd_clk_desc *desc)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct regmap *regmap;
|
||||
|
||||
if (of_find_property(node, "sprd,syscon", NULL)) {
|
||||
|
@ -49,6 +50,13 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
|
|||
pr_err("%s: failed to get syscon regmap\n", __func__);
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
} else if (of_device_is_compatible(of_get_parent(dev->of_node),
|
||||
"syscon")) {
|
||||
regmap = device_node_to_regmap(of_get_parent(dev->of_node));
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(dev, "failed to get regmap from its parent.\n");
|
||||
return PTR_ERR(regmap);
|
||||
}
|
||||
} else {
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
|
|
|
@ -18,26 +18,43 @@ struct sprd_comp {
|
|||
struct sprd_clk_common common;
|
||||
};
|
||||
|
||||
#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, _flags) \
|
||||
#define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, \
|
||||
_flags, _fn) \
|
||||
struct sprd_comp _struct = { \
|
||||
.mux = _SPRD_MUX_CLK(_mshift, _mwidth, _table), \
|
||||
.div = _SPRD_DIV_CLK(_dshift, _dwidth), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parent, \
|
||||
&sprd_comp_ops, \
|
||||
_flags), \
|
||||
.hw.init = _fn(_name, _parent, \
|
||||
&sprd_comp_ops, _flags), \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
|
||||
_mwidth, _dshift, _dwidth, _flags) \
|
||||
SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, \
|
||||
NULL, _mshift, _mwidth, \
|
||||
_dshift, _dwidth, _flags)
|
||||
#define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, _flags) \
|
||||
SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, \
|
||||
_flags, CLK_HW_INIT_PARENTS)
|
||||
|
||||
#define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \
|
||||
_mwidth, _dshift, _dwidth, _flags) \
|
||||
SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, _flags)
|
||||
|
||||
#define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \
|
||||
_mshift, _mwidth, _dshift, \
|
||||
_dwidth, _flags) \
|
||||
SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, \
|
||||
_flags, CLK_HW_INIT_PARENTS_DATA)
|
||||
|
||||
#define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \
|
||||
_mwidth, _dshift, _dwidth, _flags) \
|
||||
SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
|
||||
_mshift, _mwidth, _dshift, _dwidth, \
|
||||
_flags)
|
||||
|
||||
static inline struct sprd_comp *hw_to_sprd_comp(const struct clk_hw *hw)
|
||||
{
|
||||
|
|
|
@ -35,20 +35,28 @@ struct sprd_div {
|
|||
struct sprd_clk_common common;
|
||||
};
|
||||
|
||||
#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _flags) \
|
||||
#define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _flags, _fn) \
|
||||
struct sprd_div _struct = { \
|
||||
.div = _SPRD_DIV_CLK(_shift, _width), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&sprd_div_ops, \
|
||||
_flags), \
|
||||
.hw.init = _fn(_name, _parent, \
|
||||
&sprd_div_ops, _flags), \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _flags) \
|
||||
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _flags, CLK_HW_INIT)
|
||||
|
||||
#define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _flags) \
|
||||
SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _flags, CLK_HW_INIT_HW)
|
||||
|
||||
static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw)
|
||||
{
|
||||
struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
|
||||
|
|
|
@ -79,6 +79,17 @@ static int sprd_sc_gate_enable(struct clk_hw *hw)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sprd_pll_sc_gate_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct sprd_gate *sg = hw_to_sprd_gate(hw);
|
||||
|
||||
clk_sc_gate_toggle(sg, true);
|
||||
udelay(sg->udelay);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sprd_gate_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct sprd_gate *sg = hw_to_sprd_gate(hw);
|
||||
|
@ -109,3 +120,9 @@ const struct clk_ops sprd_sc_gate_ops = {
|
|||
};
|
||||
EXPORT_SYMBOL_GPL(sprd_sc_gate_ops);
|
||||
|
||||
const struct clk_ops sprd_pll_sc_gate_ops = {
|
||||
.unprepare = sprd_sc_gate_disable,
|
||||
.prepare = sprd_pll_sc_gate_prepare,
|
||||
.is_enabled = sprd_gate_is_enabled,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops);
|
||||
|
|
|
@ -14,37 +14,136 @@ struct sprd_gate {
|
|||
u32 enable_mask;
|
||||
u16 flags;
|
||||
u16 sc_offset;
|
||||
u16 udelay;
|
||||
|
||||
struct sprd_clk_common common;
|
||||
};
|
||||
|
||||
#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
_enable_mask, _flags, _gate_flags, _ops) \
|
||||
#define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay, _ops, _fn) \
|
||||
struct sprd_gate _struct = { \
|
||||
.enable_mask = _enable_mask, \
|
||||
.sc_offset = _sc_offset, \
|
||||
.flags = _gate_flags, \
|
||||
.udelay = _udelay, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
_ops, \
|
||||
_flags), \
|
||||
.hw.init = _fn(_name, _parent, \
|
||||
_ops, _flags), \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay, _ops) \
|
||||
SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay, _ops, CLK_HW_INIT)
|
||||
|
||||
#define SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
_enable_mask, _flags, _gate_flags, _ops) \
|
||||
SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, 0, _ops)
|
||||
|
||||
#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
_enable_mask, _flags, _gate_flags) \
|
||||
SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
_enable_mask, _flags, _gate_flags, \
|
||||
&sprd_sc_gate_ops)
|
||||
|
||||
#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \
|
||||
_enable_mask, _flags, _gate_flags) \
|
||||
SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
|
||||
_enable_mask, _flags, _gate_flags, \
|
||||
&sprd_gate_ops)
|
||||
|
||||
#define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
_enable_mask, _flags, _gate_flags) \
|
||||
SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
#define SPRD_PLL_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \
|
||||
_enable_mask, _flags, _gate_flags, \
|
||||
&sprd_sc_gate_ops)
|
||||
_udelay) \
|
||||
SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay, \
|
||||
&sprd_pll_sc_gate_ops)
|
||||
|
||||
|
||||
#define SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, \
|
||||
_flags, _gate_flags, \
|
||||
_udelay, _ops) \
|
||||
SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay, _ops, \
|
||||
CLK_HW_INIT_HW)
|
||||
|
||||
#define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _ops) \
|
||||
SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, \
|
||||
_flags, _gate_flags, 0, _ops)
|
||||
|
||||
#define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags) \
|
||||
SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, &sprd_sc_gate_ops)
|
||||
|
||||
#define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \
|
||||
_enable_mask, _flags, _gate_flags) \
|
||||
SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, 0, \
|
||||
_enable_mask, _flags, _gate_flags, \
|
||||
&sprd_gate_ops)
|
||||
|
||||
#define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay) \
|
||||
SPRD_SC_GATE_CLK_HW_OPS_UDELAY(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, \
|
||||
_flags, _gate_flags, _udelay, \
|
||||
&sprd_pll_sc_gate_ops)
|
||||
|
||||
#define SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \
|
||||
_reg, _sc_offset, \
|
||||
_enable_mask, _flags, \
|
||||
_gate_flags, _udelay, _ops) \
|
||||
SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay, _ops, \
|
||||
CLK_HW_INIT_FW_NAME)
|
||||
|
||||
#define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _ops) \
|
||||
SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \
|
||||
_reg, _sc_offset, \
|
||||
_enable_mask, _flags, \
|
||||
_gate_flags, 0, _ops)
|
||||
|
||||
#define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags) \
|
||||
SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, &sprd_sc_gate_ops)
|
||||
|
||||
#define SPRD_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \
|
||||
_enable_mask, _flags, _gate_flags) \
|
||||
SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, 0, \
|
||||
_enable_mask, _flags, _gate_flags, \
|
||||
&sprd_gate_ops)
|
||||
|
||||
#define SPRD_PLL_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \
|
||||
_sc_offset, _enable_mask, _flags, \
|
||||
_gate_flags, _udelay) \
|
||||
SPRD_SC_GATE_CLK_FW_NAME_OPS_UDELAY(_struct, _name, _parent, \
|
||||
_reg, _sc_offset, \
|
||||
_enable_mask, _flags, \
|
||||
_gate_flags, _udelay, \
|
||||
&sprd_pll_sc_gate_ops)
|
||||
|
||||
static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
|
||||
{
|
||||
|
@ -55,5 +154,6 @@ static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)
|
|||
|
||||
extern const struct clk_ops sprd_gate_ops;
|
||||
extern const struct clk_ops sprd_sc_gate_ops;
|
||||
extern const struct clk_ops sprd_pll_sc_gate_ops;
|
||||
|
||||
#endif /* _SPRD_GATE_H_ */
|
||||
|
|
|
@ -36,26 +36,40 @@ struct sprd_mux {
|
|||
.table = _table, \
|
||||
}
|
||||
|
||||
#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, \
|
||||
_flags) \
|
||||
#define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _flags, _fn) \
|
||||
struct sprd_mux _struct = { \
|
||||
.mux = _SPRD_MUX_CLK(_shift, _width, _table), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parents, \
|
||||
&sprd_mux_ops, \
|
||||
_flags), \
|
||||
.hw.init = _fn(_name, _parents, \
|
||||
&sprd_mux_ops, _flags), \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _flags) \
|
||||
SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _flags, \
|
||||
CLK_HW_INIT_PARENTS)
|
||||
|
||||
#define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \
|
||||
_shift, _width, _flags) \
|
||||
SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
|
||||
_reg, _shift, _width, _flags)
|
||||
|
||||
#define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _flags) \
|
||||
SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _flags, \
|
||||
CLK_HW_INIT_PARENTS_DATA)
|
||||
|
||||
#define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \
|
||||
_shift, _width, _flags) \
|
||||
SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
|
||||
_reg, _shift, _width, _flags)
|
||||
|
||||
static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)
|
||||
{
|
||||
struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
|
||||
|
|
|
@ -87,11 +87,12 @@ static u32 pll_get_ibias(u64 rate, const u64 *table)
|
|||
{
|
||||
u32 i, num = table[0];
|
||||
|
||||
for (i = 1; i < num + 1; i++)
|
||||
if (rate <= table[i])
|
||||
/* table[0] indicates the number of items in this table */
|
||||
for (i = 0; i < num; i++)
|
||||
if (rate <= table[i + 1])
|
||||
break;
|
||||
|
||||
return (i == num + 1) ? num : i;
|
||||
return i == num ? num - 1 : i;
|
||||
}
|
||||
|
||||
static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
|
||||
|
|
|
@ -61,27 +61,33 @@ struct sprd_pll {
|
|||
struct sprd_clk_common common;
|
||||
};
|
||||
|
||||
#define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \
|
||||
_regs_num, _itable, _factors, \
|
||||
_udelay, _k1, _k2, _fflag, \
|
||||
_fvco, _fn) \
|
||||
struct sprd_pll _struct = { \
|
||||
.regs_num = _regs_num, \
|
||||
.itable = _itable, \
|
||||
.factors = _factors, \
|
||||
.udelay = _udelay, \
|
||||
.k1 = _k1, \
|
||||
.k2 = _k2, \
|
||||
.fflag = _fflag, \
|
||||
.fvco = _fvco, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.reg = _reg, \
|
||||
.hw.init = _fn(_name, _parent, \
|
||||
&sprd_pll_ops, 0),\
|
||||
}, \
|
||||
}
|
||||
|
||||
#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
|
||||
_regs_num, _itable, _factors, \
|
||||
_udelay, _k1, _k2, _fflag, _fvco) \
|
||||
struct sprd_pll _struct = { \
|
||||
.regs_num = _regs_num, \
|
||||
.itable = _itable, \
|
||||
.factors = _factors, \
|
||||
.udelay = _udelay, \
|
||||
.k1 = _k1, \
|
||||
.k2 = _k2, \
|
||||
.fflag = _fflag, \
|
||||
.fvco = _fvco, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&sprd_pll_ops, \
|
||||
0), \
|
||||
}, \
|
||||
}
|
||||
SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
|
||||
_itable, _factors, _udelay, _k1, _k2, \
|
||||
_fflag, _fvco, CLK_HW_INIT)
|
||||
|
||||
#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \
|
||||
_regs_num, _itable, _factors, \
|
||||
|
@ -96,6 +102,19 @@ struct sprd_pll {
|
|||
_regs_num, _itable, _factors, \
|
||||
_udelay, 1000, 1000, 0, 0)
|
||||
|
||||
#define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \
|
||||
_itable, _factors, _udelay, _k1, _k2, \
|
||||
_fflag, _fvco) \
|
||||
SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
|
||||
_itable, _factors, _udelay, _k1, _k2, \
|
||||
_fflag, _fvco, CLK_HW_INIT_FW_NAME)
|
||||
|
||||
#define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \
|
||||
_factors, _udelay, _k1, _k2, _fflag, _fvco) \
|
||||
SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
|
||||
_itable, _factors, _udelay, _k1, _k2, \
|
||||
_fflag, _fvco, CLK_HW_INIT_HW)
|
||||
|
||||
static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw)
|
||||
{
|
||||
struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);
|
||||
|
|
1772
drivers/clk/sprd/sc9863a-clk.c
Normal file
1772
drivers/clk/sprd/sc9863a-clk.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -12,7 +12,6 @@ obj-y += clk-sdmmc-mux.o
|
|||
obj-y += clk-super.o
|
||||
obj-y += clk-tegra-audio.o
|
||||
obj-y += clk-tegra-periph.o
|
||||
obj-y += clk-tegra-pmc.o
|
||||
obj-y += clk-tegra-fixed.o
|
||||
obj-y += clk-tegra-super-gen4.o
|
||||
obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
|
||||
|
|
|
@ -32,7 +32,6 @@ enum clk_id {
|
|||
tegra_clk_audio4,
|
||||
tegra_clk_audio4_2x,
|
||||
tegra_clk_audio4_mux,
|
||||
tegra_clk_blink,
|
||||
tegra_clk_bsea,
|
||||
tegra_clk_bsev,
|
||||
tegra_clk_cclk_g,
|
||||
|
@ -44,14 +43,9 @@ enum clk_id {
|
|||
tegra_clk_clk72Mhz,
|
||||
tegra_clk_clk72Mhz_8,
|
||||
tegra_clk_clk_m,
|
||||
tegra_clk_clk_m_div2,
|
||||
tegra_clk_clk_m_div4,
|
||||
tegra_clk_clk_out_1,
|
||||
tegra_clk_clk_out_1_mux,
|
||||
tegra_clk_clk_out_2,
|
||||
tegra_clk_clk_out_2_mux,
|
||||
tegra_clk_clk_out_3,
|
||||
tegra_clk_clk_out_3_mux,
|
||||
tegra_clk_osc,
|
||||
tegra_clk_osc_div2,
|
||||
tegra_clk_osc_div4,
|
||||
tegra_clk_cml0,
|
||||
tegra_clk_cml1,
|
||||
tegra_clk_csi,
|
||||
|
|
|
@ -46,7 +46,28 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
|
||||
if (!dt_clk)
|
||||
return 0;
|
||||
|
||||
osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
|
||||
*dt_clk = osc;
|
||||
|
||||
/* osc_div2 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
|
||||
0, 1, 2);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* osc_div4 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
|
||||
0, 1, 4);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
|
||||
if (!dt_clk)
|
||||
|
@ -84,22 +105,6 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
|
|||
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* clk_m_div2 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
||||
/* clk_m_div4 */
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
|
||||
if (dt_clk) {
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 4);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
}
|
||||
|
||||
void tegra_clk_osc_resume(void __iomem *clk_base)
|
||||
|
|
|
@ -1,122 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/clk/tegra.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-id.h"
|
||||
|
||||
#define PMC_CLK_OUT_CNTRL 0x1a8
|
||||
#define PMC_DPD_PADS_ORIDE 0x1c
|
||||
#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
|
||||
#define PMC_CTRL 0
|
||||
#define PMC_CTRL_BLINK_ENB 7
|
||||
#define PMC_BLINK_TIMER 0x40
|
||||
|
||||
struct pmc_clk_init_data {
|
||||
char *mux_name;
|
||||
char *gate_name;
|
||||
const char **parents;
|
||||
int num_parents;
|
||||
int mux_id;
|
||||
int gate_id;
|
||||
char *dev_name;
|
||||
u8 mux_shift;
|
||||
u8 gate_shift;
|
||||
};
|
||||
|
||||
#define PMC_CLK(_num, _mux_shift, _gate_shift)\
|
||||
{\
|
||||
.mux_name = "clk_out_" #_num "_mux",\
|
||||
.gate_name = "clk_out_" #_num,\
|
||||
.parents = clk_out ##_num ##_parents,\
|
||||
.num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
|
||||
.mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
|
||||
.gate_id = tegra_clk_clk_out_ ##_num,\
|
||||
.dev_name = "extern" #_num,\
|
||||
.mux_shift = _mux_shift,\
|
||||
.gate_shift = _gate_shift,\
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(clk_out_lock);
|
||||
|
||||
static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
|
||||
"clk_m_div4", "extern1",
|
||||
};
|
||||
|
||||
static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
|
||||
"clk_m_div4", "extern2",
|
||||
};
|
||||
|
||||
static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
|
||||
"clk_m_div4", "extern3",
|
||||
};
|
||||
|
||||
static struct pmc_clk_init_data pmc_clks[] = {
|
||||
PMC_CLK(1, 6, 2),
|
||||
PMC_CLK(2, 14, 10),
|
||||
PMC_CLK(3, 22, 18),
|
||||
};
|
||||
|
||||
void __init tegra_pmc_clk_init(void __iomem *pmc_base,
|
||||
struct tegra_clk *tegra_clks)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk **dt_clk;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
|
||||
struct pmc_clk_init_data *data;
|
||||
|
||||
data = pmc_clks + i;
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = clk_register_mux(NULL, data->mux_name, data->parents,
|
||||
data->num_parents,
|
||||
CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
|
||||
pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
|
||||
3, 0, &clk_out_lock);
|
||||
*dt_clk = clk;
|
||||
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
|
||||
if (!dt_clk)
|
||||
continue;
|
||||
|
||||
clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
|
||||
CLK_SET_RATE_PARENT,
|
||||
pmc_base + PMC_CLK_OUT_CNTRL,
|
||||
data->gate_shift, 0, &clk_out_lock);
|
||||
*dt_clk = clk;
|
||||
clk_register_clkdev(clk, data->dev_name, data->gate_name);
|
||||
}
|
||||
|
||||
/* blink */
|
||||
writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
|
||||
clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
|
||||
pmc_base + PMC_DPD_PADS_ORIDE,
|
||||
PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
|
||||
|
||||
dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
|
||||
if (!dt_clk)
|
||||
return;
|
||||
|
||||
clk = clk_register_gate(NULL, "blink", "blink_override", 0,
|
||||
pmc_base + PMC_CTRL,
|
||||
PMC_CTRL_BLINK_ENB, 0, NULL);
|
||||
clk_register_clkdev(clk, "blink", NULL);
|
||||
*dt_clk = clk;
|
||||
}
|
||||
|
|
@ -735,8 +735,9 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
|
||||
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
|
||||
|
@ -778,10 +779,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
|
||||
[tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
|
||||
[tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
|
||||
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
|
||||
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
|
||||
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
|
||||
|
@ -803,9 +800,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
|
||||
[tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
|
||||
[tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
|
||||
[tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
|
||||
[tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
|
||||
|
@ -815,8 +809,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
|
||||
|
@ -863,10 +858,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
|
||||
{ .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
|
||||
|
@ -900,17 +894,6 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
|
|||
/* clk_32k */
|
||||
clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
|
||||
clks[TEGRA114_CLK_CLK_32K] = clk;
|
||||
|
||||
/* clk_m_div2 */
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 2);
|
||||
clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
|
||||
|
||||
/* clk_m_div4 */
|
||||
clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
|
||||
CLK_SET_RATE_PARENT, 1, 4);
|
||||
clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
|
||||
|
||||
}
|
||||
|
||||
static void __init tegra114_pll_init(void __iomem *clk_base,
|
||||
|
@ -1153,11 +1136,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
@ -1359,7 +1339,6 @@ static void __init tegra114_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
|
||||
tegra114_audio_plls,
|
||||
ARRAY_SIZE(tegra114_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra114_clks);
|
||||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
|
||||
&pll_x_params);
|
||||
|
||||
|
|
|
@ -860,8 +860,9 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
|
||||
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
|
||||
|
@ -902,10 +903,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
|
||||
[tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
|
||||
[tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
|
||||
[tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
|
||||
[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
|
||||
[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
|
||||
|
@ -931,9 +928,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
|
||||
[tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
|
||||
[tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
|
||||
};
|
||||
|
||||
|
@ -941,8 +935,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
|
||||
|
@ -988,10 +983,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
|
||||
{ .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
|
||||
|
@ -1298,11 +1292,8 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
|
|||
{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
@ -1457,11 +1448,9 @@ static void __init tegra132_clock_apply_init_table(void)
|
|||
* tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most of the clocks controlled by the CAR IP block, along
|
||||
* with a few clocks controlled by the PMC IP block. Everything in
|
||||
* this function should be common to Tegra124 and Tegra132. XXX The
|
||||
* PMC clock initialization should probably be moved to PMC-specific
|
||||
* driver code. No return value.
|
||||
* Register most of the clocks controlled by the CAR IP block.
|
||||
* Everything in this function should be common to Tegra124 and Tegra132.
|
||||
* No return value.
|
||||
*/
|
||||
static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
||||
{
|
||||
|
@ -1504,7 +1493,6 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
|
||||
tegra124_audio_plls,
|
||||
ARRAY_SIZE(tegra124_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra124_clks);
|
||||
|
||||
/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
|
||||
plld_base = readl(clk_base + PLLD_BASE);
|
||||
|
@ -1516,11 +1504,11 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
|
|||
* tegra124_132_clock_init_post - clock initialization postamble for T124/T132
|
||||
* @np: struct device_node * of the DT node for the SoC CAR IP block
|
||||
*
|
||||
* Register most of the along with a few clocks controlled by the PMC
|
||||
* IP block. Everything in this function should be common to Tegra124
|
||||
* Register most of the clocks controlled by the CAR IP block.
|
||||
* Everything in this function should be common to Tegra124
|
||||
* and Tegra132. This function must be called after
|
||||
* tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
|
||||
* not be set. No return value.
|
||||
* tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
|
||||
* No return value.
|
||||
*/
|
||||
static void __init tegra124_132_clock_init_post(struct device_node *np)
|
||||
{
|
||||
|
|
|
@ -458,7 +458,6 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
|
||||
{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
|
||||
{ .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
|
||||
{ .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
|
||||
{ .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
|
||||
|
@ -537,7 +536,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
|
||||
[tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
|
||||
[tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
|
||||
[tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
|
||||
[tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
|
||||
|
@ -1031,10 +1029,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
|
||||
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
|
||||
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
|
||||
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
|
@ -1146,7 +1142,6 @@ static void __init tegra20_clock_init(struct device_node *np)
|
|||
tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
|
||||
tegra20_periph_clk_init();
|
||||
tegra20_audio_clk_init();
|
||||
tegra_pmc_clk_init(pmc_base, tegra20_clks);
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
|
||||
|
||||
|
|
|
@ -2371,8 +2371,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
|
||||
[tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
|
||||
|
@ -2417,10 +2418,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
|
||||
[tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
|
||||
[tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
|
||||
[tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
|
||||
[tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
|
||||
[tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
|
||||
|
@ -2452,9 +2449,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
|
||||
[tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
|
||||
[tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
|
||||
[tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
|
||||
[tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
|
||||
|
@ -2497,8 +2491,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
|
||||
{ .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
|
||||
{ .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
|
||||
{ .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
|
||||
{ .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
|
||||
|
@ -2540,10 +2535,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
|
||||
{ .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
|
||||
|
@ -2999,7 +2993,7 @@ static const char * const la_parents[] = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_periph tegra210_la =
|
||||
TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
|
||||
TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
|
||||
|
||||
static __init void tegra210_periph_clk_init(void __iomem *clk_base,
|
||||
void __iomem *pmc_base)
|
||||
|
@ -3448,11 +3442,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
@ -3693,7 +3684,6 @@ static void __init tegra210_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
|
||||
tegra210_audio_plls,
|
||||
ARRAY_SIZE(tegra210_audio_plls), 24576000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra210_clks);
|
||||
|
||||
/* For Tegra210, PLLD is the only source for DSIA & DSIB */
|
||||
value = readl(clk_base + PLLD_BASE);
|
||||
|
|
|
@ -569,10 +569,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
|
||||
{ .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
|
||||
{ .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
|
||||
{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
|
||||
{ .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
|
||||
{ .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
|
||||
{ .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
|
||||
{ .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
|
||||
{ .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
|
||||
{ .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
|
||||
{ .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
|
||||
|
@ -581,8 +580,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
{ .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
|
||||
{ .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
|
||||
{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
|
||||
{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
|
||||
{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
|
||||
{ .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
|
||||
{ .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
|
||||
{ .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
|
||||
{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
|
||||
{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
|
||||
{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
|
||||
|
@ -683,8 +683,9 @@ static struct tegra_devclk devclks[] __initdata = {
|
|||
static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
|
||||
[tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
|
||||
[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
|
||||
[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
|
||||
[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
|
||||
[tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
|
||||
[tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
|
||||
[tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
|
||||
[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
|
||||
[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
|
||||
[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
|
||||
|
@ -711,13 +712,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
|
|||
[tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
|
||||
[tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
|
||||
[tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
|
||||
[tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
|
||||
[tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
|
||||
[tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
|
||||
[tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
|
||||
[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
|
||||
[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
|
||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
|
||||
[tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
|
||||
[tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
|
||||
[tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
|
||||
|
@ -1227,12 +1221,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
|
|||
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
|
||||
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
|
@ -1362,7 +1352,6 @@ static void __init tegra30_clock_init(struct device_node *np)
|
|||
tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
|
||||
tegra30_audio_plls,
|
||||
ARRAY_SIZE(tegra30_audio_plls), 24000000);
|
||||
tegra_pmc_clk_init(pmc_base, tegra30_clks);
|
||||
|
||||
tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
|
||||
|
||||
|
|
|
@ -854,7 +854,6 @@ void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
|
|||
struct tegra_clk *tegra_clks,
|
||||
struct tegra_clk_pll_params *pll_params);
|
||||
|
||||
void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
|
||||
void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
|
||||
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
|
||||
unsigned long *input_freqs, unsigned int num,
|
||||
|
|
|
@ -451,5 +451,6 @@
|
|||
#define IMX7D_SNVS_CLK 442
|
||||
#define IMX7D_CAAM_CLK 443
|
||||
#define IMX7D_KPP_ROOT_CLK 444
|
||||
#define IMX7D_CLK_END 445
|
||||
#define IMX7D_PXP_CLK 445
|
||||
#define IMX7D_CLK_END 446
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
|
|
|
@ -265,6 +265,15 @@
|
|||
#define IMX8MM_SYS_PLL2_333M_CG 244
|
||||
#define IMX8MM_SYS_PLL2_500M_CG 245
|
||||
|
||||
#define IMX8MM_CLK_END 246
|
||||
#define IMX8MM_CLK_M4_CORE 246
|
||||
#define IMX8MM_CLK_VPU_CORE 247
|
||||
#define IMX8MM_CLK_GPU3D_CORE 248
|
||||
#define IMX8MM_CLK_GPU2D_CORE 249
|
||||
|
||||
#define IMX8MM_CLK_CLKO2 250
|
||||
|
||||
#define IMX8MM_CLK_A53_CORE 251
|
||||
|
||||
#define IMX8MM_CLK_END 252
|
||||
|
||||
#endif
|
||||
|
|
|
@ -228,6 +228,12 @@
|
|||
#define IMX8MN_SYS_PLL2_333M_CG 209
|
||||
#define IMX8MN_SYS_PLL2_500M_CG 210
|
||||
|
||||
#define IMX8MN_CLK_END 211
|
||||
#define IMX8MN_CLK_SNVS_ROOT 211
|
||||
#define IMX8MN_CLK_GPU_CORE 212
|
||||
#define IMX8MN_CLK_GPU_SHADER 213
|
||||
|
||||
#define IMX8MN_CLK_A53_CORE 214
|
||||
|
||||
#define IMX8MN_CLK_END 215
|
||||
|
||||
#endif
|
||||
|
|
|
@ -173,7 +173,7 @@
|
|||
#define IMX8MP_CLK_IPP_DO_CLKO1 164
|
||||
#define IMX8MP_CLK_IPP_DO_CLKO2 165
|
||||
#define IMX8MP_CLK_HDMI_FDCC_TST 166
|
||||
#define IMX8MP_CLK_HDMI_27M 167
|
||||
#define IMX8MP_CLK_HDMI_24M 167
|
||||
#define IMX8MP_CLK_HDMI_REF_266M 168
|
||||
#define IMX8MP_CLK_USDHC3 169
|
||||
#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
|
||||
|
@ -294,7 +294,8 @@
|
|||
#define IMX8MP_CLK_DRAM_ALT_ROOT 285
|
||||
#define IMX8MP_CLK_DRAM_CORE 286
|
||||
#define IMX8MP_CLK_ARM 287
|
||||
#define IMX8MP_CLK_A53_CORE 288
|
||||
|
||||
#define IMX8MP_CLK_END 288
|
||||
#define IMX8MP_CLK_END 289
|
||||
|
||||
#endif
|
||||
|
|
|
@ -424,6 +424,13 @@
|
|||
#define IMX8MQ_SYS2_PLL_500M_CG 283
|
||||
#define IMX8MQ_SYS2_PLL_1000M_CG 284
|
||||
|
||||
#define IMX8MQ_CLK_END 285
|
||||
#define IMX8MQ_CLK_GPU_CORE 285
|
||||
#define IMX8MQ_CLK_GPU_SHADER 286
|
||||
#define IMX8MQ_CLK_M4_CORE 287
|
||||
#define IMX8MQ_CLK_VPU_CORE 288
|
||||
|
||||
#define IMX8MQ_CLK_A53_CORE 289
|
||||
|
||||
#define IMX8MQ_CLK_END 290
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H
|
||||
|
@ -132,6 +132,11 @@
|
|||
#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
|
||||
#define GCC_VIDEO_THROTTLE_AXI_CLK 123
|
||||
#define GCC_VIDEO_XO_CLK 124
|
||||
#define GCC_MSS_CFG_AHB_CLK 125
|
||||
#define GCC_MSS_MFAB_AXIS_CLK 126
|
||||
#define GCC_MSS_NAV_AXI_CLK 127
|
||||
#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
|
||||
#define GCC_MSS_SNOC_AXI_CLK 129
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 0
|
||||
|
|
|
@ -240,4 +240,8 @@
|
|||
#define GCC_USB30_SEC_BCR 27
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
|
||||
|
||||
/* GCC GDSCRs */
|
||||
#define USB30_PRIM_GDSC 4
|
||||
#define USB30_SEC_GDSC 5
|
||||
|
||||
#endif
|
||||
|
|
271
include/dt-bindings/clock/qcom,gcc-sm8250.h
Normal file
271
include/dt-bindings/clock/qcom,gcc-sm8250.h
Normal file
|
@ -0,0 +1,271 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
|
||||
|
||||
/* GCC clocks */
|
||||
#define GPLL0 0
|
||||
#define GPLL0_OUT_EVEN 1
|
||||
#define GPLL4 2
|
||||
#define GPLL9 3
|
||||
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
|
||||
#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
|
||||
#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
|
||||
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
|
||||
#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
|
||||
#define GCC_BOOT_ROM_AHB_CLK 9
|
||||
#define GCC_CAMERA_AHB_CLK 10
|
||||
#define GCC_CAMERA_HF_AXI_CLK 11
|
||||
#define GCC_CAMERA_SF_AXI_CLK 12
|
||||
#define GCC_CAMERA_XO_CLK 13
|
||||
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
|
||||
#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
|
||||
#define GCC_CPUSS_AHB_CLK 16
|
||||
#define GCC_CPUSS_AHB_CLK_SRC 17
|
||||
#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
|
||||
#define GCC_CPUSS_DVM_BUS_CLK 19
|
||||
#define GCC_CPUSS_RBCPR_CLK 20
|
||||
#define GCC_DDRSS_GPU_AXI_CLK 21
|
||||
#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
|
||||
#define GCC_DISP_AHB_CLK 23
|
||||
#define GCC_DISP_HF_AXI_CLK 24
|
||||
#define GCC_DISP_SF_AXI_CLK 25
|
||||
#define GCC_DISP_XO_CLK 26
|
||||
#define GCC_GP1_CLK 27
|
||||
#define GCC_GP1_CLK_SRC 28
|
||||
#define GCC_GP2_CLK 29
|
||||
#define GCC_GP2_CLK_SRC 30
|
||||
#define GCC_GP3_CLK 31
|
||||
#define GCC_GP3_CLK_SRC 32
|
||||
#define GCC_GPU_CFG_AHB_CLK 33
|
||||
#define GCC_GPU_GPLL0_CLK_SRC 34
|
||||
#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
|
||||
#define GCC_GPU_IREF_EN 36
|
||||
#define GCC_GPU_MEMNOC_GFX_CLK 37
|
||||
#define GCC_GPU_SNOC_DVM_GFX_CLK 38
|
||||
#define GCC_NPU_AXI_CLK 39
|
||||
#define GCC_NPU_BWMON_AXI_CLK 40
|
||||
#define GCC_NPU_BWMON_CFG_AHB_CLK 41
|
||||
#define GCC_NPU_CFG_AHB_CLK 42
|
||||
#define GCC_NPU_DMA_CLK 43
|
||||
#define GCC_NPU_GPLL0_CLK_SRC 44
|
||||
#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
|
||||
#define GCC_PCIE0_PHY_REFGEN_CLK 46
|
||||
#define GCC_PCIE1_PHY_REFGEN_CLK 47
|
||||
#define GCC_PCIE2_PHY_REFGEN_CLK 48
|
||||
#define GCC_PCIE_0_AUX_CLK 49
|
||||
#define GCC_PCIE_0_AUX_CLK_SRC 50
|
||||
#define GCC_PCIE_0_CFG_AHB_CLK 51
|
||||
#define GCC_PCIE_0_MSTR_AXI_CLK 52
|
||||
#define GCC_PCIE_0_PIPE_CLK 53
|
||||
#define GCC_PCIE_0_SLV_AXI_CLK 54
|
||||
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
|
||||
#define GCC_PCIE_1_AUX_CLK 56
|
||||
#define GCC_PCIE_1_AUX_CLK_SRC 57
|
||||
#define GCC_PCIE_1_CFG_AHB_CLK 58
|
||||
#define GCC_PCIE_1_MSTR_AXI_CLK 59
|
||||
#define GCC_PCIE_1_PIPE_CLK 60
|
||||
#define GCC_PCIE_1_SLV_AXI_CLK 61
|
||||
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
|
||||
#define GCC_PCIE_2_AUX_CLK 63
|
||||
#define GCC_PCIE_2_AUX_CLK_SRC 64
|
||||
#define GCC_PCIE_2_CFG_AHB_CLK 65
|
||||
#define GCC_PCIE_2_MSTR_AXI_CLK 66
|
||||
#define GCC_PCIE_2_PIPE_CLK 67
|
||||
#define GCC_PCIE_2_SLV_AXI_CLK 68
|
||||
#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
|
||||
#define GCC_PCIE_MDM_CLKREF_EN 70
|
||||
#define GCC_PCIE_PHY_AUX_CLK 71
|
||||
#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
|
||||
#define GCC_PCIE_WIFI_CLKREF_EN 73
|
||||
#define GCC_PCIE_WIGIG_CLKREF_EN 74
|
||||
#define GCC_PDM2_CLK 75
|
||||
#define GCC_PDM2_CLK_SRC 76
|
||||
#define GCC_PDM_AHB_CLK 77
|
||||
#define GCC_PDM_XO4_CLK 78
|
||||
#define GCC_PRNG_AHB_CLK 79
|
||||
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
|
||||
#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
|
||||
#define GCC_QMIP_DISP_AHB_CLK 82
|
||||
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
|
||||
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
|
||||
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
|
||||
#define GCC_QUPV3_WRAP0_CORE_CLK 86
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK 87
|
||||
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK 89
|
||||
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK 91
|
||||
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK 93
|
||||
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK 95
|
||||
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK 97
|
||||
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK 99
|
||||
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK 101
|
||||
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
|
||||
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
|
||||
#define GCC_QUPV3_WRAP1_CORE_CLK 104
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK 105
|
||||
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK 107
|
||||
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK 109
|
||||
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK 111
|
||||
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK 113
|
||||
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK 115
|
||||
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
|
||||
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
|
||||
#define GCC_QUPV3_WRAP2_CORE_CLK 118
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK 119
|
||||
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK 121
|
||||
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK 123
|
||||
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK 125
|
||||
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK 127
|
||||
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK 129
|
||||
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
|
||||
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
|
||||
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
|
||||
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
|
||||
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
|
||||
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
|
||||
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
|
||||
#define GCC_SDCC2_AHB_CLK 137
|
||||
#define GCC_SDCC2_APPS_CLK 138
|
||||
#define GCC_SDCC2_APPS_CLK_SRC 139
|
||||
#define GCC_SDCC4_AHB_CLK 140
|
||||
#define GCC_SDCC4_APPS_CLK 141
|
||||
#define GCC_SDCC4_APPS_CLK_SRC 142
|
||||
#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
|
||||
#define GCC_TSIF_AHB_CLK 144
|
||||
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
|
||||
#define GCC_TSIF_REF_CLK 146
|
||||
#define GCC_TSIF_REF_CLK_SRC 147
|
||||
#define GCC_UFS_1X_CLKREF_EN 148
|
||||
#define GCC_UFS_CARD_AHB_CLK 149
|
||||
#define GCC_UFS_CARD_AXI_CLK 150
|
||||
#define GCC_UFS_CARD_AXI_CLK_SRC 151
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK 152
|
||||
#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK 154
|
||||
#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
|
||||
#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
|
||||
#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
|
||||
#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
|
||||
#define GCC_UFS_PHY_AHB_CLK 161
|
||||
#define GCC_UFS_PHY_AXI_CLK 162
|
||||
#define GCC_UFS_PHY_AXI_CLK_SRC 163
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK 164
|
||||
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK 166
|
||||
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
|
||||
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
|
||||
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
|
||||
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
|
||||
#define GCC_USB30_PRIM_MASTER_CLK 173
|
||||
#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
|
||||
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
|
||||
#define GCC_USB30_PRIM_SLEEP_CLK 178
|
||||
#define GCC_USB30_SEC_MASTER_CLK 179
|
||||
#define GCC_USB30_SEC_MASTER_CLK_SRC 180
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
|
||||
#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
|
||||
#define GCC_USB30_SEC_SLEEP_CLK 184
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK 185
|
||||
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
|
||||
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
|
||||
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
|
||||
#define GCC_USB3_SEC_CLKREF_EN 190
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK 191
|
||||
#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
|
||||
#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK 194
|
||||
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
|
||||
#define GCC_VIDEO_AHB_CLK 196
|
||||
#define GCC_VIDEO_AXI0_CLK 197
|
||||
#define GCC_VIDEO_AXI1_CLK 198
|
||||
#define GCC_VIDEO_XO_CLK 199
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_GPU_BCR 0
|
||||
#define GCC_MMSS_BCR 1
|
||||
#define GCC_NPU_BWMON_BCR 2
|
||||
#define GCC_NPU_BCR 3
|
||||
#define GCC_PCIE_0_BCR 4
|
||||
#define GCC_PCIE_0_LINK_DOWN_BCR 5
|
||||
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
|
||||
#define GCC_PCIE_0_PHY_BCR 7
|
||||
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
|
||||
#define GCC_PCIE_1_BCR 9
|
||||
#define GCC_PCIE_1_LINK_DOWN_BCR 10
|
||||
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
|
||||
#define GCC_PCIE_1_PHY_BCR 12
|
||||
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
|
||||
#define GCC_PCIE_2_BCR 14
|
||||
#define GCC_PCIE_2_LINK_DOWN_BCR 15
|
||||
#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
|
||||
#define GCC_PCIE_2_PHY_BCR 17
|
||||
#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
|
||||
#define GCC_PCIE_PHY_BCR 19
|
||||
#define GCC_PCIE_PHY_CFG_AHB_BCR 20
|
||||
#define GCC_PCIE_PHY_COM_BCR 21
|
||||
#define GCC_PDM_BCR 22
|
||||
#define GCC_PRNG_BCR 23
|
||||
#define GCC_QUPV3_WRAPPER_0_BCR 24
|
||||
#define GCC_QUPV3_WRAPPER_1_BCR 25
|
||||
#define GCC_QUPV3_WRAPPER_2_BCR 26
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 27
|
||||
#define GCC_QUSB2PHY_SEC_BCR 28
|
||||
#define GCC_SDCC2_BCR 29
|
||||
#define GCC_SDCC4_BCR 30
|
||||
#define GCC_TSIF_BCR 31
|
||||
#define GCC_UFS_CARD_BCR 32
|
||||
#define GCC_UFS_PHY_BCR 33
|
||||
#define GCC_USB30_PRIM_BCR 34
|
||||
#define GCC_USB30_SEC_BCR 35
|
||||
#define GCC_USB3_DP_PHY_PRIM_BCR 36
|
||||
#define GCC_USB3_DP_PHY_SEC_BCR 37
|
||||
#define GCC_USB3_PHY_PRIM_BCR 38
|
||||
#define GCC_USB3_PHY_SEC_BCR 39
|
||||
#define GCC_USB3PHY_PHY_PRIM_BCR 40
|
||||
#define GCC_USB3PHY_PHY_SEC_BCR 41
|
||||
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
|
||||
#define GCC_VIDEO_AXI0_CLK_ARES 43
|
||||
#define GCC_VIDEO_AXI1_CLK_ARES 44
|
||||
|
||||
/* GCC power domains */
|
||||
#define PCIE_0_GDSC 0
|
||||
#define PCIE_1_GDSC 1
|
||||
#define PCIE_2_GDSC 2
|
||||
#define UFS_CARD_GDSC 3
|
||||
#define UFS_PHY_GDSC 4
|
||||
#define USB30_PRIM_GDSC 5
|
||||
#define USB30_SEC_GDSC 6
|
||||
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
|
||||
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
|
||||
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
|
||||
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
|
||||
|
||||
#endif
|
|
@ -15,7 +15,8 @@
|
|||
#define GPU_CC_CXO_CLK 6
|
||||
#define GPU_CC_GMU_CLK_SRC 7
|
||||
|
||||
/* CAM_CC GDSCRs */
|
||||
/* GPU_CC GDSCRs */
|
||||
#define CX_GDSC 0
|
||||
#define GX_GDSC 1
|
||||
|
||||
#endif
|
||||
|
|
12
include/dt-bindings/clock/qcom,mss-sc7180.h
Normal file
12
include/dt-bindings/clock/qcom,mss-sc7180.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
|
||||
#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
|
||||
|
||||
#define MSS_AXI_CRYPTO_CLK 0
|
||||
#define MSS_AXI_NAV_CLK 1
|
||||
|
||||
#endif
|
|
@ -37,6 +37,10 @@
|
|||
#define RPM_XO_A0 27
|
||||
#define RPM_XO_A1 28
|
||||
#define RPM_XO_A2 29
|
||||
#define RPM_NSS_FABRIC_0_CLK 30
|
||||
#define RPM_NSS_FABRIC_0_A_CLK 31
|
||||
#define RPM_NSS_FABRIC_1_CLK 32
|
||||
#define RPM_NSS_FABRIC_1_A_CLK 33
|
||||
|
||||
/* SMD RPM clocks */
|
||||
#define RPM_SMD_XO_CLK_SRC 0
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
|
||||
/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. */
|
||||
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
|
||||
|
@ -19,5 +19,7 @@
|
|||
#define RPMH_RF_CLK3 10
|
||||
#define RPMH_RF_CLK3_A 11
|
||||
#define RPMH_IPA_CLK 12
|
||||
#define RPMH_LN_BB_CLK1 13
|
||||
#define RPMH_LN_BB_CLK1_A 14
|
||||
|
||||
#endif
|
||||
|
|
334
include/dt-bindings/clock/sprd,sc9863a-clk.h
Normal file
334
include/dt-bindings/clock/sprd,sc9863a-clk.h
Normal file
|
@ -0,0 +1,334 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Unisoc SC9863A platform clocks
|
||||
*
|
||||
* Copyright (C) 2019, Unisoc Communications Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SC9863A_H_
|
||||
#define _DT_BINDINGS_CLK_SC9863A_H_
|
||||
|
||||
#define CLK_MPLL0_GATE 0
|
||||
#define CLK_DPLL0_GATE 1
|
||||
#define CLK_LPLL_GATE 2
|
||||
#define CLK_GPLL_GATE 3
|
||||
#define CLK_DPLL1_GATE 4
|
||||
#define CLK_MPLL1_GATE 5
|
||||
#define CLK_MPLL2_GATE 6
|
||||
#define CLK_ISPPLL_GATE 7
|
||||
#define CLK_PMU_APB_NUM (CLK_ISPPLL_GATE + 1)
|
||||
|
||||
#define CLK_AUDIO_GATE 0
|
||||
#define CLK_RPLL 1
|
||||
#define CLK_RPLL_390M 2
|
||||
#define CLK_RPLL_260M 3
|
||||
#define CLK_RPLL_195M 4
|
||||
#define CLK_RPLL_26M 5
|
||||
#define CLK_ANLG_PHY_G5_NUM (CLK_RPLL_26M + 1)
|
||||
|
||||
#define CLK_TWPLL 0
|
||||
#define CLK_TWPLL_768M 1
|
||||
#define CLK_TWPLL_384M 2
|
||||
#define CLK_TWPLL_192M 3
|
||||
#define CLK_TWPLL_96M 4
|
||||
#define CLK_TWPLL_48M 5
|
||||
#define CLK_TWPLL_24M 6
|
||||
#define CLK_TWPLL_12M 7
|
||||
#define CLK_TWPLL_512M 8
|
||||
#define CLK_TWPLL_256M 9
|
||||
#define CLK_TWPLL_128M 10
|
||||
#define CLK_TWPLL_64M 11
|
||||
#define CLK_TWPLL_307M2 12
|
||||
#define CLK_TWPLL_219M4 13
|
||||
#define CLK_TWPLL_170M6 14
|
||||
#define CLK_TWPLL_153M6 15
|
||||
#define CLK_TWPLL_76M8 16
|
||||
#define CLK_TWPLL_51M2 17
|
||||
#define CLK_TWPLL_38M4 18
|
||||
#define CLK_TWPLL_19M2 19
|
||||
#define CLK_LPLL 20
|
||||
#define CLK_LPLL_409M6 21
|
||||
#define CLK_LPLL_245M76 22
|
||||
#define CLK_GPLL 23
|
||||
#define CLK_ISPPLL 24
|
||||
#define CLK_ISPPLL_468M 25
|
||||
#define CLK_ANLG_PHY_G1_NUM (CLK_ISPPLL_468M + 1)
|
||||
|
||||
#define CLK_DPLL0 0
|
||||
#define CLK_DPLL1 1
|
||||
#define CLK_DPLL0_933M 2
|
||||
#define CLK_DPLL0_622M3 3
|
||||
#define CLK_DPLL0_400M 4
|
||||
#define CLK_DPLL0_266M7 5
|
||||
#define CLK_DPLL0_123M1 6
|
||||
#define CLK_DPLL0_50M 7
|
||||
#define CLK_ANLG_PHY_G7_NUM (CLK_DPLL0_50M + 1)
|
||||
|
||||
#define CLK_MPLL0 0
|
||||
#define CLK_MPLL1 1
|
||||
#define CLK_MPLL2 2
|
||||
#define CLK_MPLL2_675M 3
|
||||
#define CLK_ANLG_PHY_G4_NUM (CLK_MPLL2_675M + 1)
|
||||
|
||||
#define CLK_AP_APB 0
|
||||
#define CLK_AP_CE 1
|
||||
#define CLK_NANDC_ECC 2
|
||||
#define CLK_NANDC_26M 3
|
||||
#define CLK_EMMC_32K 4
|
||||
#define CLK_SDIO0_32K 5
|
||||
#define CLK_SDIO1_32K 6
|
||||
#define CLK_SDIO2_32K 7
|
||||
#define CLK_OTG_UTMI 8
|
||||
#define CLK_AP_UART0 9
|
||||
#define CLK_AP_UART1 10
|
||||
#define CLK_AP_UART2 11
|
||||
#define CLK_AP_UART3 12
|
||||
#define CLK_AP_UART4 13
|
||||
#define CLK_AP_I2C0 14
|
||||
#define CLK_AP_I2C1 15
|
||||
#define CLK_AP_I2C2 16
|
||||
#define CLK_AP_I2C3 17
|
||||
#define CLK_AP_I2C4 18
|
||||
#define CLK_AP_I2C5 19
|
||||
#define CLK_AP_I2C6 20
|
||||
#define CLK_AP_SPI0 21
|
||||
#define CLK_AP_SPI1 22
|
||||
#define CLK_AP_SPI2 23
|
||||
#define CLK_AP_SPI3 24
|
||||
#define CLK_AP_IIS0 25
|
||||
#define CLK_AP_IIS1 26
|
||||
#define CLK_AP_IIS2 27
|
||||
#define CLK_SIM0 28
|
||||
#define CLK_SIM0_32K 29
|
||||
#define CLK_AP_CLK_NUM (CLK_SIM0_32K + 1)
|
||||
|
||||
#define CLK_13M 0
|
||||
#define CLK_6M5 1
|
||||
#define CLK_4M3 2
|
||||
#define CLK_2M 3
|
||||
#define CLK_250K 4
|
||||
#define CLK_RCO_25M 5
|
||||
#define CLK_RCO_4M 6
|
||||
#define CLK_RCO_2M 7
|
||||
#define CLK_EMC 8
|
||||
#define CLK_AON_APB 9
|
||||
#define CLK_ADI 10
|
||||
#define CLK_AUX0 11
|
||||
#define CLK_AUX1 12
|
||||
#define CLK_AUX2 13
|
||||
#define CLK_PROBE 14
|
||||
#define CLK_PWM0 15
|
||||
#define CLK_PWM1 16
|
||||
#define CLK_PWM2 17
|
||||
#define CLK_AON_THM 18
|
||||
#define CLK_AUDIF 19
|
||||
#define CLK_CPU_DAP 20
|
||||
#define CLK_CPU_TS 21
|
||||
#define CLK_DJTAG_TCK 22
|
||||
#define CLK_EMC_REF 23
|
||||
#define CLK_CSSYS 24
|
||||
#define CLK_AON_PMU 25
|
||||
#define CLK_PMU_26M 26
|
||||
#define CLK_AON_TMR 27
|
||||
#define CLK_POWER_CPU 28
|
||||
#define CLK_AP_AXI 29
|
||||
#define CLK_SDIO0_2X 30
|
||||
#define CLK_SDIO1_2X 31
|
||||
#define CLK_SDIO2_2X 32
|
||||
#define CLK_EMMC_2X 33
|
||||
#define CLK_DPU 34
|
||||
#define CLK_DPU_DPI 35
|
||||
#define CLK_OTG_REF 36
|
||||
#define CLK_SDPHY_APB 37
|
||||
#define CLK_ALG_IO_APB 38
|
||||
#define CLK_GPU_CORE 39
|
||||
#define CLK_GPU_SOC 40
|
||||
#define CLK_MM_EMC 41
|
||||
#define CLK_MM_AHB 42
|
||||
#define CLK_BPC 43
|
||||
#define CLK_DCAM_IF 44
|
||||
#define CLK_ISP 45
|
||||
#define CLK_JPG 46
|
||||
#define CLK_CPP 47
|
||||
#define CLK_SENSOR0 48
|
||||
#define CLK_SENSOR1 49
|
||||
#define CLK_SENSOR2 50
|
||||
#define CLK_MM_VEMC 51
|
||||
#define CLK_MM_VAHB 52
|
||||
#define CLK_VSP 53
|
||||
#define CLK_CORE0 54
|
||||
#define CLK_CORE1 55
|
||||
#define CLK_CORE2 56
|
||||
#define CLK_CORE3 57
|
||||
#define CLK_CORE4 58
|
||||
#define CLK_CORE5 59
|
||||
#define CLK_CORE6 60
|
||||
#define CLK_CORE7 61
|
||||
#define CLK_SCU 62
|
||||
#define CLK_ACE 63
|
||||
#define CLK_AXI_PERIPH 64
|
||||
#define CLK_AXI_ACP 65
|
||||
#define CLK_ATB 66
|
||||
#define CLK_DEBUG_APB 67
|
||||
#define CLK_GIC 68
|
||||
#define CLK_PERIPH 69
|
||||
#define CLK_AON_CLK_NUM (CLK_VSP + 1)
|
||||
|
||||
#define CLK_OTG_EB 0
|
||||
#define CLK_DMA_EB 1
|
||||
#define CLK_CE_EB 2
|
||||
#define CLK_NANDC_EB 3
|
||||
#define CLK_SDIO0_EB 4
|
||||
#define CLK_SDIO1_EB 5
|
||||
#define CLK_SDIO2_EB 6
|
||||
#define CLK_EMMC_EB 7
|
||||
#define CLK_EMMC_32K_EB 8
|
||||
#define CLK_SDIO0_32K_EB 9
|
||||
#define CLK_SDIO1_32K_EB 10
|
||||
#define CLK_SDIO2_32K_EB 11
|
||||
#define CLK_NANDC_26M_EB 12
|
||||
#define CLK_DMA_EB2 13
|
||||
#define CLK_CE_EB2 14
|
||||
#define CLK_AP_AHB_GATE_NUM (CLK_CE_EB2 + 1)
|
||||
|
||||
#define CLK_GPIO_EB 0
|
||||
#define CLK_PWM0_EB 1
|
||||
#define CLK_PWM1_EB 2
|
||||
#define CLK_PWM2_EB 3
|
||||
#define CLK_PWM3_EB 4
|
||||
#define CLK_KPD_EB 5
|
||||
#define CLK_AON_SYST_EB 6
|
||||
#define CLK_AP_SYST_EB 7
|
||||
#define CLK_AON_TMR_EB 8
|
||||
#define CLK_EFUSE_EB 9
|
||||
#define CLK_EIC_EB 10
|
||||
#define CLK_INTC_EB 11
|
||||
#define CLK_ADI_EB 12
|
||||
#define CLK_AUDIF_EB 13
|
||||
#define CLK_AUD_EB 14
|
||||
#define CLK_VBC_EB 15
|
||||
#define CLK_PIN_EB 16
|
||||
#define CLK_AP_WDG_EB 17
|
||||
#define CLK_MM_EB 18
|
||||
#define CLK_AON_APB_CKG_EB 19
|
||||
#define CLK_CA53_TS0_EB 20
|
||||
#define CLK_CA53_TS1_EB 21
|
||||
#define CLK_CS53_DAP_EB 22
|
||||
#define CLK_PMU_EB 23
|
||||
#define CLK_THM_EB 24
|
||||
#define CLK_AUX0_EB 25
|
||||
#define CLK_AUX1_EB 26
|
||||
#define CLK_AUX2_EB 27
|
||||
#define CLK_PROBE_EB 28
|
||||
#define CLK_EMC_REF_EB 29
|
||||
#define CLK_CA53_WDG_EB 30
|
||||
#define CLK_AP_TMR1_EB 31
|
||||
#define CLK_AP_TMR2_EB 32
|
||||
#define CLK_DISP_EMC_EB 33
|
||||
#define CLK_ZIP_EMC_EB 34
|
||||
#define CLK_GSP_EMC_EB 35
|
||||
#define CLK_MM_VSP_EB 36
|
||||
#define CLK_MDAR_EB 37
|
||||
#define CLK_RTC4M0_CAL_EB 38
|
||||
#define CLK_RTC4M1_CAL_EB 39
|
||||
#define CLK_DJTAG_EB 40
|
||||
#define CLK_MBOX_EB 41
|
||||
#define CLK_AON_DMA_EB 42
|
||||
#define CLK_AON_APB_DEF_EB 43
|
||||
#define CLK_CA5_TS0_EB 44
|
||||
#define CLK_DBG_EB 45
|
||||
#define CLK_DBG_EMC_EB 46
|
||||
#define CLK_CROSS_TRIG_EB 47
|
||||
#define CLK_SERDES_DPHY_EB 48
|
||||
#define CLK_ARCH_RTC_EB 49
|
||||
#define CLK_KPD_RTC_EB 50
|
||||
#define CLK_AON_SYST_RTC_EB 51
|
||||
#define CLK_AP_SYST_RTC_EB 52
|
||||
#define CLK_AON_TMR_RTC_EB 53
|
||||
#define CLK_AP_TMR0_RTC_EB 54
|
||||
#define CLK_EIC_RTC_EB 55
|
||||
#define CLK_EIC_RTCDV5_EB 56
|
||||
#define CLK_AP_WDG_RTC_EB 57
|
||||
#define CLK_CA53_WDG_RTC_EB 58
|
||||
#define CLK_THM_RTC_EB 59
|
||||
#define CLK_ATHMA_RTC_EB 60
|
||||
#define CLK_GTHMA_RTC_EB 61
|
||||
#define CLK_ATHMA_RTC_A_EB 62
|
||||
#define CLK_GTHMA_RTC_A_EB 63
|
||||
#define CLK_AP_TMR1_RTC_EB 64
|
||||
#define CLK_AP_TMR2_RTC_EB 65
|
||||
#define CLK_DXCO_LC_RTC_EB 66
|
||||
#define CLK_BB_CAL_RTC_EB 67
|
||||
#define CLK_GNU_EB 68
|
||||
#define CLK_DISP_EB 69
|
||||
#define CLK_MM_EMC_EB 70
|
||||
#define CLK_POWER_CPU_EB 71
|
||||
#define CLK_HW_I2C_EB 72
|
||||
#define CLK_MM_VSP_EMC_EB 73
|
||||
#define CLK_VSP_EB 74
|
||||
#define CLK_CSSYS_EB 75
|
||||
#define CLK_DMC_EB 76
|
||||
#define CLK_ROSC_EB 77
|
||||
#define CLK_S_D_CFG_EB 78
|
||||
#define CLK_S_D_REF_EB 79
|
||||
#define CLK_B_DMA_EB 80
|
||||
#define CLK_ANLG_EB 81
|
||||
#define CLK_ANLG_APB_EB 82
|
||||
#define CLK_BSMTMR_EB 83
|
||||
#define CLK_AP_AXI_EB 84
|
||||
#define CLK_AP_INTC0_EB 85
|
||||
#define CLK_AP_INTC1_EB 86
|
||||
#define CLK_AP_INTC2_EB 87
|
||||
#define CLK_AP_INTC3_EB 88
|
||||
#define CLK_AP_INTC4_EB 89
|
||||
#define CLK_AP_INTC5_EB 90
|
||||
#define CLK_SCC_EB 91
|
||||
#define CLK_DPHY_CFG_EB 92
|
||||
#define CLK_DPHY_REF_EB 93
|
||||
#define CLK_CPHY_CFG_EB 94
|
||||
#define CLK_OTG_REF_EB 95
|
||||
#define CLK_SERDES_EB 96
|
||||
#define CLK_AON_AP_EMC_EB 97
|
||||
#define CLK_AON_APB_GATE_NUM (CLK_AON_AP_EMC_EB + 1)
|
||||
|
||||
#define CLK_MAHB_CKG_EB 0
|
||||
#define CLK_MDCAM_EB 1
|
||||
#define CLK_MISP_EB 2
|
||||
#define CLK_MAHBCSI_EB 3
|
||||
#define CLK_MCSI_S_EB 4
|
||||
#define CLK_MCSI_T_EB 5
|
||||
#define CLK_DCAM_AXI_EB 6
|
||||
#define CLK_ISP_AXI_EB 7
|
||||
#define CLK_MCSI_EB 8
|
||||
#define CLK_MCSI_S_CKG_EB 9
|
||||
#define CLK_MCSI_T_CKG_EB 10
|
||||
#define CLK_SENSOR0_EB 11
|
||||
#define CLK_SENSOR1_EB 12
|
||||
#define CLK_SENSOR2_EB 13
|
||||
#define CLK_MCPHY_CFG_EB 14
|
||||
#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1)
|
||||
|
||||
#define CLK_SIM0_EB 0
|
||||
#define CLK_IIS0_EB 1
|
||||
#define CLK_IIS1_EB 2
|
||||
#define CLK_IIS2_EB 3
|
||||
#define CLK_SPI0_EB 4
|
||||
#define CLK_SPI1_EB 5
|
||||
#define CLK_SPI2_EB 6
|
||||
#define CLK_I2C0_EB 7
|
||||
#define CLK_I2C1_EB 8
|
||||
#define CLK_I2C2_EB 9
|
||||
#define CLK_I2C3_EB 10
|
||||
#define CLK_I2C4_EB 11
|
||||
#define CLK_UART0_EB 12
|
||||
#define CLK_UART1_EB 13
|
||||
#define CLK_UART2_EB 14
|
||||
#define CLK_UART3_EB 15
|
||||
#define CLK_UART4_EB 16
|
||||
#define CLK_SIM0_32K_EB 17
|
||||
#define CLK_SPI3_EB 18
|
||||
#define CLK_I2C5_EB 19
|
||||
#define CLK_I2C6_EB 20
|
||||
#define CLK_AP_APB_GATE_NUM (CLK_I2C6_EB + 1)
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SC9863A_H_ */
|
|
@ -228,6 +228,8 @@
|
|||
#define TEGRA114_CLK_CLK_M 201
|
||||
#define TEGRA114_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA114_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA114_CLK_OSC_DIV2 202
|
||||
#define TEGRA114_CLK_OSC_DIV4 203
|
||||
#define TEGRA114_CLK_PLL_REF 204
|
||||
#define TEGRA114_CLK_PLL_C 205
|
||||
#define TEGRA114_CLK_PLL_C_OUT1 206
|
||||
|
@ -274,7 +276,7 @@
|
|||
#define TEGRA114_CLK_CLK_OUT_2 246
|
||||
#define TEGRA114_CLK_CLK_OUT_3 247
|
||||
#define TEGRA114_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA114_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA114_CLK_XUSB_HOST_SRC 252
|
||||
|
|
|
@ -227,6 +227,8 @@
|
|||
#define TEGRA124_CLK_CLK_M 201
|
||||
#define TEGRA124_CLK_CLK_M_DIV2 202
|
||||
#define TEGRA124_CLK_CLK_M_DIV4 203
|
||||
#define TEGRA124_CLK_OSC_DIV2 202
|
||||
#define TEGRA124_CLK_OSC_DIV4 203
|
||||
#define TEGRA124_CLK_PLL_REF 204
|
||||
#define TEGRA124_CLK_PLL_C 205
|
||||
#define TEGRA124_CLK_PLL_C_OUT1 206
|
||||
|
@ -273,7 +275,7 @@
|
|||
#define TEGRA124_CLK_CLK_OUT_2 246
|
||||
#define TEGRA124_CLK_CLK_OUT_3 247
|
||||
#define TEGRA124_CLK_BLINK 248
|
||||
/* 249 */
|
||||
#define TEGRA124_CLK_OSC 249
|
||||
/* 250 */
|
||||
/* 251 */
|
||||
#define TEGRA124_CLK_XUSB_HOST_SRC 252
|
||||
|
|
|
@ -262,6 +262,8 @@
|
|||
#define TEGRA210_CLK_CLK_M 233
|
||||
#define TEGRA210_CLK_CLK_M_DIV2 234
|
||||
#define TEGRA210_CLK_CLK_M_DIV4 235
|
||||
#define TEGRA210_CLK_OSC_DIV2 234
|
||||
#define TEGRA210_CLK_OSC_DIV4 235
|
||||
#define TEGRA210_CLK_PLL_REF 236
|
||||
#define TEGRA210_CLK_PLL_C 237
|
||||
#define TEGRA210_CLK_PLL_C_OUT1 238
|
||||
|
@ -355,7 +357,7 @@
|
|||
#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
|
||||
#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
|
||||
/* 325 */
|
||||
/* 326 */
|
||||
#define TEGRA210_CLK_OSC 326
|
||||
/* 327 */
|
||||
/* 328 */
|
||||
/* 329 */
|
||||
|
|
|
@ -196,6 +196,8 @@
|
|||
#define TEGRA30_CLK_CLK_M 171
|
||||
#define TEGRA30_CLK_CLK_M_DIV2 172
|
||||
#define TEGRA30_CLK_CLK_M_DIV4 173
|
||||
#define TEGRA30_CLK_OSC_DIV2 172
|
||||
#define TEGRA30_CLK_OSC_DIV4 173
|
||||
#define TEGRA30_CLK_PLL_REF 174
|
||||
#define TEGRA30_CLK_PLL_C 175
|
||||
#define TEGRA30_CLK_PLL_C_OUT1 176
|
||||
|
@ -243,7 +245,7 @@
|
|||
#define TEGRA30_CLK_HCLK 217
|
||||
#define TEGRA30_CLK_PCLK 218
|
||||
/* 219 */
|
||||
/* 220 */
|
||||
#define TEGRA30_CLK_OSC 220
|
||||
/* 221 */
|
||||
/* 222 */
|
||||
/* 223 */
|
||||
|
|
16
include/dt-bindings/soc/tegra-pmc.h
Normal file
16
include/dt-bindings/soc/tegra-pmc.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
|
||||
#define _DT_BINDINGS_SOC_TEGRA_PMC_H
|
||||
|
||||
#define TEGRA_PMC_CLK_OUT_1 0
|
||||
#define TEGRA_PMC_CLK_OUT_2 1
|
||||
#define TEGRA_PMC_CLK_OUT_3 2
|
||||
#define TEGRA_PMC_CLK_BLINK 3
|
||||
|
||||
#define TEGRA_PMC_CLK_MAX 4
|
||||
|
||||
#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */
|
Loading…
Reference in a new issue