b43: N-PHY: update general workarounds
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>hifive-unleashed-5.1
Rafał Miłecki
John W. Linville
parent
991a0987d9
commit
28fd7daabf
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@ -246,110 +246,6 @@ static void b43_nphy_tables_init(struct b43_wldev *dev)
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b43_nphy_rev3plus_tables_init(dev);
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}
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static void b43_nphy_workarounds(struct b43_wldev *dev)
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{
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struct b43_phy *phy = &dev->phy;
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unsigned int i;
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b43_phy_set(dev, B43_NPHY_IQFLIP,
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B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
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if (1 /* FIXME band is 2.4GHz */) {
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b43_phy_set(dev, B43_NPHY_CLASSCTL,
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B43_NPHY_CLASSCTL_CCKEN);
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} else {
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b43_phy_mask(dev, B43_NPHY_CLASSCTL,
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~B43_NPHY_CLASSCTL_CCKEN);
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}
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b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
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b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
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/* Fixup some tables */
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b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
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b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
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b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
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b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
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b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
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b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
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b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
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//TODO set RF sequence
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/* Set narrowband clip threshold */
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b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
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b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
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/* Set wideband clip 2 threshold */
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b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
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~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
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21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
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~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
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21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
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/* Set Clip 2 detect */
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b43_phy_set(dev, B43_NPHY_C1_CGAINI,
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B43_NPHY_C1_CGAINI_CL2DETECT);
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b43_phy_set(dev, B43_NPHY_C2_CGAINI,
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B43_NPHY_C2_CGAINI_CL2DETECT);
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if (0 /*FIXME*/) {
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/* Set dwell lengths */
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b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
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b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
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b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
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b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
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/* Set gain backoff */
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b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
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~B43_NPHY_C1_CGAINI_GAINBKOFF,
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1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
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~B43_NPHY_C2_CGAINI_GAINBKOFF,
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1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
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/* Set HPVGA2 index */
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b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
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~B43_NPHY_C1_INITGAIN_HPVGA2,
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6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
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~B43_NPHY_C2_INITGAIN_HPVGA2,
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6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
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//FIXME verify that the specs really mean to use autoinc here.
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for (i = 0; i < 3; i++)
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b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
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}
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/* Set minimum gain value */
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b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
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~B43_NPHY_C1_MINGAIN,
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23 << B43_NPHY_C1_MINGAIN_SHIFT);
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b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
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~B43_NPHY_C2_MINGAIN,
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23 << B43_NPHY_C2_MINGAIN_SHIFT);
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if (phy->rev < 2) {
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b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
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~B43_NPHY_SCRAM_SIGCTL_SCM);
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}
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/* Set phase track alpha and beta */
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b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
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b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
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b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
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b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
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b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
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b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
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static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
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{
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@ -816,6 +712,117 @@ static void b43_nphy_stop_playback(struct b43_wldev *dev)
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b43_nphy_stay_in_carrier_search(dev, 0);
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
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static void b43_nphy_workarounds(struct b43_wldev *dev)
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{
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struct ssb_bus *bus = dev->dev->bus;
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struct b43_phy *phy = &dev->phy;
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struct b43_phy_n *nphy = phy->n;
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u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
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u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
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u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
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u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
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b43_nphy_classifier(dev, 1, 0);
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else
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b43_nphy_classifier(dev, 1, 1);
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if (nphy->hang_avoid)
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b43_nphy_stay_in_carrier_search(dev, 1);
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b43_phy_set(dev, B43_NPHY_IQFLIP,
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B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
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if (dev->phy.rev >= 3) {
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/* TODO */
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} else {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
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nphy->band5g_pwrgain) {
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b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
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b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
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} else {
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b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
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b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
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}
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/* TODO: convert to b43_ntab_write? */
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
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if (dev->phy.rev < 2) {
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
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b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
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}
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
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b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
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if (bus->sprom.boardflags2_lo & 0x100 &&
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bus->boardinfo.type == 0x8B) {
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delays1[0] = 0x1;
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delays1[5] = 0x14;
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}
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/*TODO:b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);*/
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/*TODO:b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);*/
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/*TODO:b43_nphy_gain_crtl_workarounds(dev);*/
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if (dev->phy.rev < 2) {
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if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
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; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
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} else if (dev->phy.rev == 2) {
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b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
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b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
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}
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if (dev->phy.rev < 2)
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b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
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~B43_NPHY_SCRAM_SIGCTL_SCM);
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/* Set phase track alpha and beta */
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b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
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b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
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b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
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b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
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b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
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b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
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b43_phy_mask(dev, B43_NPHY_PIL_DW1,
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(u16)~B43_NPHY_PIL_DW_64QAM);
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b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
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b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
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b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
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if (dev->phy.rev == 2)
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b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
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B43_NPHY_FINERX2_CGC_DECGC);
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}
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if (nphy->hang_avoid)
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b43_nphy_stay_in_carrier_search(dev, 0);
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}
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/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
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static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
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bool test)
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@ -976,6 +976,10 @@ struct b43_phy_n {
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s32 preamble_override;
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u32 bb_mult_save;
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bool gain_boost;
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bool elna_gain_config;
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bool band5g_pwrgain;
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u8 mphase_cal_phase_id;
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u16 mphase_txcal_cmdidx;
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u16 mphase_txcal_numcmds;
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