ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level handling code and is hardwired to the local timers (hence lacking a registration interface). Instead, switch the low handling to the normal SPI handling code. PPIs are handled by the handle_percpu_devid_irq flow. This also allows the removal of some duplicated code. Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: David Brown <davidb@codeaurora.org> Tested-by: David Brown <davidb@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>hifive-unleashed-5.1
Marc Zyngier
parent
88b6fc8c57
commit
292b293cee
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@ -28,10 +28,14 @@
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#include <linux/smp.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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#include <asm/localtimer.h>
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static DEFINE_SPINLOCK(irq_controller_lock);
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@ -255,6 +259,32 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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irq_set_chained_handler(irq, gic_handle_cascade_irq);
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}
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#ifdef CONFIG_LOCAL_TIMERS
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#define gic_ppi_handler percpu_timer_handler
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#else
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static irqreturn_t gic_ppi_handler(int irq, void *dev_id)
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{
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return IRQ_NONE;
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}
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#endif
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#define PPI_IRQACT(nr) \
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{ \
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.handler = gic_ppi_handler, \
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.flags = IRQF_PERCPU | IRQF_TIMER, \
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.irq = nr, \
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.name = "PPI-" # nr, \
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}
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static struct irqaction ppi_irqaction_template[16] __initdata = {
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PPI_IRQACT(0), PPI_IRQACT(1), PPI_IRQACT(2), PPI_IRQACT(3),
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PPI_IRQACT(4), PPI_IRQACT(5), PPI_IRQACT(6), PPI_IRQACT(7),
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PPI_IRQACT(8), PPI_IRQACT(9), PPI_IRQACT(10), PPI_IRQACT(11),
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PPI_IRQACT(12), PPI_IRQACT(13), PPI_IRQACT(14), PPI_IRQACT(15),
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};
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static struct irqaction *ppi_irqaction;
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static void __init gic_dist_init(struct gic_chip_data *gic,
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unsigned int irq_start)
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{
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@ -262,6 +292,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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u32 cpumask;
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void __iomem *base = gic->dist_base;
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u32 cpu = 0;
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u32 nrppis = 0, ppi_base = 0;
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(smp_processor_id());
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@ -282,6 +313,33 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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if (gic_irqs > 1020)
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gic_irqs = 1020;
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/*
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* Nobody would be insane enough to use PPIs on a secondary
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* GIC, right?
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*/
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if (gic == &gic_data[0]) {
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nrppis = (32 - irq_start) & 31;
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/* The GIC only supports up to 16 PPIs. */
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if (nrppis > 16)
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BUG();
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ppi_base = gic->irq_offset + 32 - nrppis;
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ppi_irqaction = kmemdup(&ppi_irqaction_template[16 - nrppis],
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sizeof(*ppi_irqaction) * nrppis,
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GFP_KERNEL);
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if (nrppis && !ppi_irqaction) {
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pr_err("GIC: Can't allocate PPI memory");
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nrppis = 0;
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ppi_base = 0;
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}
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}
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pr_info("Configuring GIC with %d sources (%d PPIs)\n",
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gic_irqs, (gic == &gic_data[0]) ? nrppis : 0);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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@ -317,7 +375,22 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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/*
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* Setup the Linux IRQ subsystem.
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*/
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for (i = irq_start; i < irq_limit; i++) {
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for (i = 0; i < nrppis; i++) {
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int ppi = i + ppi_base;
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int err;
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irq_set_percpu_devid(ppi);
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irq_set_chip_and_handler(ppi, &gic_chip,
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handle_percpu_devid_irq);
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irq_set_chip_data(ppi, gic);
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set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN);
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err = setup_percpu_irq(ppi, &ppi_irqaction[i]);
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if (err)
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pr_err("GIC: can't setup PPI%d (%d)\n", ppi, err);
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}
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for (i = irq_start + nrppis; i < irq_limit; i++) {
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irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
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irq_set_chip_data(i, gic);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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@ -25,13 +25,6 @@
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movne r1, sp
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adrne lr, BSYM(1b)
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bne do_IPI
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#ifdef CONFIG_LOCAL_TIMERS
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test_for_ltirq r0, r2, r6, lr
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movne r0, sp
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adrne lr, BSYM(1b)
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bne do_local_timer
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#endif
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#endif
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9997:
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.endm
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@ -9,9 +9,6 @@
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typedef struct {
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unsigned int __softirq_pending;
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#ifdef CONFIG_LOCAL_TIMERS
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unsigned int local_timer_irqs;
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#endif
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#ifdef CONFIG_SMP
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unsigned int ipi_irqs[NR_IPI];
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#endif
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@ -22,15 +22,11 @@
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 16-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an interrupt if it's
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* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
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*
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* A simple read from the controller will tell us the number of the highest
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* priority enabled interrupt. We then just need to check whether it is in the
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* valid range for an IRQ (30-1020 inclusive).
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@ -43,7 +39,7 @@
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmp \irqnr, #15
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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@ -62,14 +58,3 @@
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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@ -10,6 +10,8 @@
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#ifndef __ASM_ARM_LOCALTIMER_H
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#define __ASM_ARM_LOCALTIMER_H
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#include <linux/interrupt.h>
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struct clock_event_device;
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/*
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@ -18,14 +20,9 @@ struct clock_event_device;
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void percpu_timer_setup(void);
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/*
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* Called from assembly, this is the local timer IRQ handler
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* Per-cpu timer IRQ handler
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*/
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asmlinkage void do_local_timer(struct pt_regs *);
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/*
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* Called from C code
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*/
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void handle_local_timer(struct pt_regs *);
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irqreturn_t percpu_timer_handler(int irq, void *dev_id);
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#ifdef CONFIG_LOCAL_TIMERS
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@ -99,9 +99,4 @@ extern void platform_cpu_enable(unsigned int cpu);
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extern void arch_send_call_function_single_ipi(int cpu);
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extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
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/*
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* show local interrupt info
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*/
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extern void show_local_irqs(struct seq_file *, int);
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#endif /* ifndef __ASM_ARM_SMP_H */
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@ -58,9 +58,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)
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#endif
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#ifdef CONFIG_SMP
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show_ipi_list(p, prec);
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#endif
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#ifdef CONFIG_LOCAL_TIMERS
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show_local_irqs(p, prec);
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#endif
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seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
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return 0;
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@ -457,10 +457,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
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for (i = 0; i < NR_IPI; i++)
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sum += __get_irq_stat(cpu, ipi_irqs[i]);
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#ifdef CONFIG_LOCAL_TIMERS
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sum += __get_irq_stat(cpu, local_timer_irqs);
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#endif
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return sum;
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}
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@ -478,34 +474,16 @@ static void ipi_timer(void)
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}
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#ifdef CONFIG_LOCAL_TIMERS
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asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
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irqreturn_t percpu_timer_handler(int irq, void *dev_id)
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{
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handle_local_timer(regs);
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}
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void handle_local_timer(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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int cpu = smp_processor_id();
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struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
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if (local_timer_ack()) {
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__inc_irq_stat(cpu, local_timer_irqs);
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ipi_timer();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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set_irq_regs(old_regs);
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}
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void show_local_irqs(struct seq_file *p, int prec)
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{
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unsigned int cpu;
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seq_printf(p, "%*s: ", prec, "LOC");
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for_each_present_cpu(cpu)
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seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs));
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seq_printf(p, " Local timer interrupts\n");
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return IRQ_NONE;
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}
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#endif
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@ -55,7 +55,7 @@
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmp \irqnr, #15
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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@ -76,8 +76,3 @@
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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.endm
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@ -36,8 +36,6 @@ static void __init msm8x60_map_io(void)
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static void __init msm8x60_init_irq(void)
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{
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unsigned int i;
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gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
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(void *)MSM_QGIC_CPU_BASE);
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@ -49,15 +47,6 @@ static void __init msm8x60_init_irq(void)
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*/
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if (!machine_is_msm8x60_sim())
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writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
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/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
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* as they are configured as level, which does not play nice with
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* handle_percpu_irq.
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*/
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for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
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if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
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irq_set_handler(i, handle_percpu_irq);
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}
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}
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static void __init msm8x60_init(void)
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@ -8,81 +8,10 @@
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/entry-macro-gic.S>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =gic_cpu_base_addr
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ldr \base, [\base]
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Migrated the code from ARM MP port to be more consistent
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* with interrupt processing , the following still holds true
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* however, all interrupts are treated the same regardless of
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* if they are local IPI or PPI
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*
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* Interrupts 0-15 are IPI
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* 16-31 are PPI
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* (16-18 are the timers)
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* A simple read from the controller will tell us the number of the
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* highest priority enabled interrupt. We then just need to check
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* whether it is in the valid range for an IRQ (0-1020 inclusive).
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*
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* Base ARM code assumes that the local (private) peripheral interrupts
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* are not valid, we treat them differently, in that the privates are
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* handled like normal shared interrupts with the exception that only
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* one processor can register the interrupt and the handler must be
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* the same for all processors.
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
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9-0 =int # */
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bic \irqnr, \irqstat, #0x1c00 @mask src
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cmp \irqnr, #15
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ldr \tmp, =1021
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt on the
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* controller, since this requires the original irqstat value which
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* we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #16
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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@ -78,7 +78,7 @@
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4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmp \irqnr, #15
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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@ -101,18 +101,6 @@
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it cs
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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itt eq
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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#endif /* CONFIG_SMP */
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#else /* MULTI_OMAP2 */
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@ -51,7 +51,4 @@
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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.endm
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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.endm
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||||
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||||
arch_irq_handler shmobile_handle_irq_intc
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@ -27,8 +27,5 @@
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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.endm
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||||
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||||
.macro test_for_ltirq, irqnr, irqstat, base, tmp
|
||||
.endm
|
||||
|
||||
.macro arch_ret_to_user, tmp1, tmp2
|
||||
.endm
|
||||
|
|
|
|||
Loading…
Reference in New Issue