drm/nv50-nvc0: tidy evo object creation some more
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>hifive-unleashed-5.1
Ben Skeggs
parent
60f60bf1bc
commit
292deb7a3b
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@ -62,4 +62,11 @@ void nv50_display_destroy(struct drm_device *dev);
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int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
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int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
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int nv50_evo_init(struct drm_device *dev);
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void nv50_evo_fini(struct drm_device *dev);
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void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
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u64 size);
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int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype,
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u64 base, u64 size, struct nouveau_gpuobj **);
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#endif /* __NV50_DISPLAY_H__ */
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@ -48,12 +48,34 @@ nv50_evo_channel_del(struct nouveau_channel **pevo)
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kfree(evo);
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}
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int
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nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
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u32 tile_flags, u32 magic_flags, u32 offset, u32 limit,
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u32 flags5)
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void
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nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size)
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{
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struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
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u32 flags5;
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if (dev_priv->chipset < 0xc0) {
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/* not supported on 0x50, specified in format mthd */
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if (dev_priv->chipset == 0x50)
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memtype = 0;
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flags5 = 0x00010000;
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} else {
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if (memtype & 0x80000000)
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flags5 = 0x00000000; /* large pages */
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else
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flags5 = 0x00020000;
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}
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nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM,
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NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0);
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nv_wo32(obj, 0x14, flags5);
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dev_priv->engine.instmem.flush(obj->dev);
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}
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int
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nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
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u64 base, u64 size, struct nouveau_gpuobj **pobj)
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{
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struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
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struct nv50_display *disp = nv50_display(evo->dev);
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struct nouveau_gpuobj *obj = NULL;
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int ret;
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@ -63,21 +85,17 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
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return ret;
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obj->engine = NVOBJ_ENGINE_DISPLAY;
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nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
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nv_wo32(obj, 4, limit);
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nv_wo32(obj, 8, offset);
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nv_wo32(obj, 12, 0x00000000);
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nv_wo32(obj, 16, 0x00000000);
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nv_wo32(obj, 20, flags5);
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dev_priv->engine.instmem.flush(evo->dev);
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nv50_evo_dmaobj_init(obj, memtype, base, size);
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ret = nouveau_ramht_insert(evo, name, obj);
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ret = nouveau_ramht_insert(evo, handle, obj);
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if (ret)
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goto out;
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if (pobj)
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nouveau_gpuobj_ref(obj, pobj);
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out:
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nouveau_gpuobj_ref(NULL, &obj);
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if (ret) {
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return ret;
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}
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return 0;
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return ret;
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}
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static int
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@ -265,49 +283,33 @@ nv50_evo_create(struct drm_device *dev)
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, 0x3d, NvEvoSync, 0, 0x19,
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disp->ntfy->vinst, disp->ntfy->vinst +
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disp->ntfy->size, 0x00010000);
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
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disp->ntfy->vinst, disp->ntfy->size, NULL);
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if (ret)
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goto err;
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/* create some default objects for the scanout memtypes we support */
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if (dev_priv->card_type >= NV_C0) {
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19,
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0, 0xffffffff, 0x00000000);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
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0, dev_priv->vram_size, 0x00020000);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
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0, dev_priv->vram_size, 0x00000000);
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if (ret)
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goto err;
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} else {
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
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0, 0xffffffff, 0x00010000);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
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(dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
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0, 0xffffffff, 0x00010000);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
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0, dev_priv->vram_size, 0x00010000);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
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0, dev_priv->vram_size, 0x00010000);
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if (ret)
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goto err;
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}
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
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(dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00),
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0, dev_priv->vram_size, NULL);
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if (ret)
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goto err;
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return 0;
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@ -27,12 +27,6 @@
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#ifndef __NV50_EVO_H__
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#define __NV50_EVO_H__
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int nv50_evo_init(struct drm_device *dev);
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void nv50_evo_fini(struct drm_device *dev);
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int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 class, u32 name,
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u32 tile_flags, u32 magic_flags,
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u32 offset, u32 limit, u32 flags5);
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#define NV50_EVO_UPDATE 0x00000080
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#define NV50_EVO_UNK84 0x00000084
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#define NV50_EVO_UNK84_NOTIFY 0x40000000
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