drm/i915: Make ->update_primary_plane infallible
Way back we've used this to reject framebuffers with unsupported pixel formats. But since the modesetting reorg with the compute config stage we reject those much earlier and just BUG() in this callback. So switch to a void return type. Reviewed-by: Akash Goel <akash.goel@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -471,9 +471,9 @@ struct drm_i915_display_funcs {
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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uint32_t flags);
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int (*update_primary_plane)(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y);
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void (*update_primary_plane)(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y);
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void (*hpd_irq_setup)(struct drm_device *dev);
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/* clock updates for mode set */
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/* cursor updates */
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@ -2330,9 +2330,9 @@ static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
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}
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}
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static int i9xx_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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static void i9xx_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -2418,13 +2418,11 @@ static int i9xx_update_primary_plane(struct drm_crtc *crtc,
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} else
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I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
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POSTING_READ(reg);
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return 0;
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}
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static int ironlake_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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static void ironlake_update_primary_plane(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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int x, int y)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -2502,8 +2500,6 @@ static int ironlake_update_primary_plane(struct drm_crtc *crtc,
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I915_WRITE(DSPLINOFF(plane), linear_offset);
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}
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POSTING_READ(reg);
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return 0;
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}
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/* Assume fb object is pinned & idle & fenced and just update base pointers */
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@ -2518,7 +2514,9 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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dev_priv->display.disable_fbc(dev);
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intel_increase_pllclock(crtc);
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return dev_priv->display.update_primary_plane(crtc, fb, x, y);
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dev_priv->display.update_primary_plane(crtc, fb, x, y);
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return 0;
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}
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void intel_display_handle_reset(struct drm_device *dev)
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@ -2677,14 +2675,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
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}
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ret = dev_priv->display.update_primary_plane(crtc, fb, x, y);
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if (ret) {
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mutex_lock(&dev->struct_mutex);
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intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
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mutex_unlock(&dev->struct_mutex);
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DRM_ERROR("failed to update base address\n");
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return ret;
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}
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dev_priv->display.update_primary_plane(crtc, fb, x, y);
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old_fb = crtc->primary->fb;
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crtc->primary->fb = fb;
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