drm/i915: Move the hw semaphore initialisation from GEM to the engine
Since we are setting engine local values that are tied to the hardware, move it out of i915_gem_init_seqno() into the intel_ring_init_seqno() backend, next to where the other hw semaphore registers are written. v2: Make the explanatory comment about always resetting the semaphores to 0 irrespective of the value of the reset seqno. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460010558-10705-4-git-send-email-chris@chris-wilson.co.uk
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@ -2468,7 +2468,7 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_engine_cs *engine;
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int ret, j;
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int ret;
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/* Carefully retire all requests without writing to the rings */
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for_each_engine(engine, dev_priv) {
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@ -2479,13 +2479,9 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
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i915_gem_retire_requests(dev);
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/* Finally reset hw state */
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for_each_engine(engine, dev_priv) {
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for_each_engine(engine, dev_priv)
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intel_ring_init_seqno(engine, seqno);
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for (j = 0; j < ARRAY_SIZE(engine->semaphore.sync_seqno); j++)
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engine->semaphore.sync_seqno[j] = 0;
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}
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return 0;
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}
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@ -2552,14 +2552,25 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
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{
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struct drm_i915_private *dev_priv = to_i915(engine->dev);
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/* Our semaphore implementation is strictly monotonic (i.e. we proceed
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* so long as the semaphore value in the register/page is greater
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* than the sync value), so whenever we reset the seqno,
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* so long as we reset the tracking semaphore value to 0, it will
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* always be before the next request's seqno. If we don't reset
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* the semaphore value, then when the seqno moves backwards all
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* future waits will complete instantly (causing rendering corruption).
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*/
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if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
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I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
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I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
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if (HAS_VEBOX(dev_priv))
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I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
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}
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memset(engine->semaphore.sync_seqno, 0,
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sizeof(engine->semaphore.sync_seqno));
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engine->set_seqno(engine, seqno);
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engine->hangcheck.seqno = seqno;
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}
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