powerpc/eeh: Use cached capability for log dump
When calling into eeh_gather_pci_data() on pSeries platform, we possiblly don't have pci_dev instance yet, but eeh_dev is always ready. So we use cached capability from eeh_dev instead of pci_dev for log dump there. In order to keep things unified, we also cache PCI capability positions to eeh_dev for PowerNV as well. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -99,7 +99,9 @@ struct eeh_dev {
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int config_addr; /* Config address */
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int pe_config_addr; /* PE config address */
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u32 config_space[16]; /* Saved PCI config space */
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u8 pcie_cap; /* Saved PCIe capability */
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int pcix_cap; /* Saved PCIx capability */
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int pcie_cap; /* Saved PCIe capability */
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int aer_cap; /* Saved AER capability */
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struct eeh_pe *pe; /* Associated PE */
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struct list_head list; /* Form link list in the PE */
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struct pci_controller *phb; /* Associated PHB */
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@ -145,7 +145,6 @@ static struct eeh_stats eeh_stats;
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static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
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{
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struct device_node *dn = eeh_dev_to_of_node(edev);
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struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
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u32 cfg;
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int cap, i;
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int n = 0;
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@ -161,13 +160,8 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
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n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
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pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
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if (!dev) {
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pr_warn("EEH: no PCI device for this of node\n");
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return n;
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}
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/* Gather bridge-specific registers */
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if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
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if (edev->mode & EEH_DEV_BRIDGE) {
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eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg);
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n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
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pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
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@ -178,7 +172,7 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
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}
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/* Dump out the PCI-X command and status regs */
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cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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cap = edev->pcix_cap;
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if (cap) {
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eeh_ops->read_config(dn, cap, 4, &cfg);
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n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
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@ -189,28 +183,29 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
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pr_warn("EEH: PCI-X status: %08x\n", cfg);
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}
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/* If PCI-E capable, dump PCI-E cap 10, and the AER */
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if (pci_is_pcie(dev)) {
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/* If PCI-E capable, dump PCI-E cap 10 */
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cap = edev->pcie_cap;
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if (cap) {
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n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
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pr_warn("EEH: PCI-E capabilities and status follow:\n");
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for (i=0; i<=8; i++) {
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eeh_ops->read_config(dn, dev->pcie_cap+4*i, 4, &cfg);
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eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
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n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
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pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg);
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}
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}
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cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (cap) {
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n += scnprintf(buf+n, len-n, "pci-e AER:\n");
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pr_warn("EEH: PCI-E AER capability register "
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"set follows:\n");
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/* If AER capable, dump it */
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cap = edev->aer_cap;
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if (cap) {
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n += scnprintf(buf+n, len-n, "pci-e AER:\n");
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pr_warn("EEH: PCI-E AER capability register set follows:\n");
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for (i=0; i<14; i++) {
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eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
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n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
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pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg);
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}
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for (i=0; i<14; i++) {
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eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
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n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
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pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg);
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}
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}
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@ -126,6 +126,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
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edev->mode &= 0xFFFFFF00;
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
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edev->mode |= EEH_DEV_BRIDGE;
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edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (pci_is_pcie(dev)) {
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edev->pcie_cap = pci_pcie_cap(dev);
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@ -133,6 +134,9 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
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edev->mode |= EEH_DEV_ROOT_PORT;
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else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
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edev->mode |= EEH_DEV_DS_PORT;
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edev->aer_cap = pci_find_ext_capability(dev,
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PCI_EXT_CAP_ID_ERR);
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}
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edev->config_addr = ((dev->bus->number << 8) | dev->devfn);
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@ -175,6 +175,36 @@ static int pseries_eeh_find_cap(struct device_node *dn, int cap)
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return 0;
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}
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static int pseries_eeh_find_ecap(struct device_node *dn, int cap)
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{
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struct pci_dn *pdn = PCI_DN(dn);
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struct eeh_dev *edev = of_node_to_eeh_dev(dn);
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u32 header;
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int pos = 256;
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int ttl = (4096 - 256) / 8;
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if (!edev || !edev->pcie_cap)
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return 0;
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if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
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return 0;
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else if (!header)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap && pos)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < 256)
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break;
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if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
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break;
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}
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return 0;
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}
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/**
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* pseries_eeh_of_probe - EEH probe on the given device
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* @dn: OF node
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@ -220,7 +250,9 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
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* or PCIe switch downstream port.
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*/
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edev->class_code = class_code;
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edev->pcix_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_PCIX);
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edev->pcie_cap = pseries_eeh_find_cap(dn, PCI_CAP_ID_EXP);
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edev->aer_cap = pseries_eeh_find_ecap(dn, PCI_EXT_CAP_ID_ERR);
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edev->mode &= 0xFFFFFF00;
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if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
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edev->mode |= EEH_DEV_BRIDGE;
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