igb: Remove GS40G specific defines/functions
The I210 internal PHY can be accessed just as well with the access
functions shared by 82580, I350, and I354 devices. A side effect of
relying on the common functions, is that I210 cable length support
is folded back into the common case which effectively reverts the
following commit:
commit 59f301046b
Author: Carolyn Wyborny <carolyn.wyborny@intel.com>
Date: Wed Oct 10 04:42:59 2012 +0000
igb: Update get cable length function for i210/i211
Cc: Carolyn Wyborny <carolyn.wyborny@intel.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
386164d9b3
commit
2a3cdead8b
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@ -45,8 +45,6 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *);
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static s32 igb_init_hw_82575(struct e1000_hw *);
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static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
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static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
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static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
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static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
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static s32 igb_reset_hw_82575(struct e1000_hw *);
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static s32 igb_reset_hw_82580(struct e1000_hw *);
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static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
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@ -205,13 +203,10 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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phy->ops.read_reg = igb_read_phy_reg_82580;
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phy->ops.write_reg = igb_write_phy_reg_82580;
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break;
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case e1000_i210:
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case e1000_i211:
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phy->ops.read_reg = igb_read_phy_reg_gs40g;
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phy->ops.write_reg = igb_write_phy_reg_gs40g;
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phy->ops.read_reg = igb_read_phy_reg_82580;
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phy->ops.write_reg = igb_write_phy_reg_82580;
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break;
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default:
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phy->ops.read_reg = igb_read_phy_reg_igp;
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@ -2153,7 +2148,7 @@ void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
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* Reads the MDI control register in the PHY at offset and stores the
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* information read to data.
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**/
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static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
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s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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s32 ret_val;
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@ -2177,7 +2172,7 @@ out:
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*
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* Writes data to MDI control register in the PHY at offset.
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**/
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static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
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s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
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{
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s32 ret_val;
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@ -861,10 +861,10 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw)
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if (ret_val)
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nvm_word = E1000_INVM_DEFAULT_AL;
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tmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;
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igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, E1000_PHY_PLL_FREQ_PAGE);
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for (i = 0; i < E1000_MAX_PLL_TRIES; i++) {
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/* check current state directly from internal PHY */
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igb_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE |
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E1000_PHY_PLL_FREQ_REG), &phy_word);
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igb_read_phy_reg_82580(hw, E1000_PHY_PLL_FREQ_REG, &phy_word);
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if ((phy_word & E1000_PHY_PLL_UNCONF)
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!= E1000_PHY_PLL_UNCONF) {
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ret_val = 0;
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@ -896,6 +896,7 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw)
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/* restore WUC register */
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wr32(E1000_WUC, wuc);
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}
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igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0);
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/* restore MDICNFG setting */
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wr32(E1000_MDICNFG, mdicnfg);
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return ret_val;
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@ -85,7 +85,7 @@ enum E1000_INVM_STRUCTURE_TYPE {
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#define E1000_PCI_PMCSR_D3 0x03
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#define E1000_MAX_PLL_TRIES 5
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#define E1000_PHY_PLL_UNCONF 0xFF
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#define E1000_PHY_PLL_FREQ_PAGE 0xFC0000
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#define E1000_PHY_PLL_FREQ_PAGE 0xFC
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#define E1000_PHY_PLL_FREQ_REG 0x000E
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#define E1000_INVM_DEFAULT_AL 0x202F
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#define E1000_INVM_AUTOLOAD 0x0A
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@ -1719,30 +1719,10 @@ s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
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u16 phy_data, phy_data2, index, default_page, is_cm;
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switch (hw->phy.id) {
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case I210_I_PHY_ID:
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/* Get cable length from PHY Cable Diagnostics Control Reg */
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ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
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(I347AT4_PCDL + phy->addr),
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&phy_data);
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if (ret_val)
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return ret_val;
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/* Check if the unit of cable length is meters or cm */
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ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
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I347AT4_PCDC, &phy_data2);
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if (ret_val)
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return ret_val;
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is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
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/* Populate the phy structure with cable length in meters */
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phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
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phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
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phy->cable_length = phy_data / (is_cm ? 100 : 1);
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break;
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case M88E1543_E_PHY_ID:
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case M88E1512_E_PHY_ID:
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case I347AT4_E_PHY_ID:
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case I210_I_PHY_ID:
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/* Remember the original page select and set it to 7 */
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ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
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&default_page);
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@ -2587,66 +2567,6 @@ out:
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return ret_val;
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}
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/**
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* igb_write_phy_reg_gs40g - Write GS40G PHY register
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* @hw: pointer to the HW structure
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* @offset: lower half is register offset to write to
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* upper half is page to use.
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* @data: data to write at register offset
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*
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* Acquires semaphore, if necessary, then writes the data to PHY register
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* at the offset. Release any acquired semaphores before exiting.
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**/
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s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
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{
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s32 ret_val;
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u16 page = offset >> GS40G_PAGE_SHIFT;
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offset = offset & GS40G_OFFSET_MASK;
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
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if (ret_val)
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goto release;
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ret_val = igb_write_phy_reg_mdic(hw, offset, data);
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release:
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hw->phy.ops.release(hw);
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return ret_val;
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}
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/**
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* igb_read_phy_reg_gs40g - Read GS40G PHY register
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* @hw: pointer to the HW structure
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* @offset: lower half is register offset to read to
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* upper half is page to use.
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* @data: data to read at register offset
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*
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* Acquires semaphore, if necessary, then reads the data in the PHY register
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* at the offset. Release any acquired semaphores before exiting.
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**/
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s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
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{
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s32 ret_val;
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u16 page = offset >> GS40G_PAGE_SHIFT;
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offset = offset & GS40G_OFFSET_MASK;
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ret_val = hw->phy.ops.acquire(hw);
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if (ret_val)
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return ret_val;
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ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
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if (ret_val)
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goto release;
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ret_val = igb_read_phy_reg_mdic(hw, offset, data);
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release:
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hw->phy.ops.release(hw);
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return ret_val;
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}
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/**
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* igb_set_master_slave_mode - Setup PHY for Master/slave mode
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* @hw: pointer to the HW structure
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@ -72,8 +72,8 @@ s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
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s32 igb_get_phy_info_82580(struct e1000_hw *hw);
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s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
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s32 igb_get_cable_length_82580(struct e1000_hw *hw);
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s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_check_polarity_m88(struct e1000_hw *hw);
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/* IGP01E1000 Specific Registers */
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@ -144,17 +144,6 @@ s32 igb_check_polarity_m88(struct e1000_hw *hw);
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#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
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/* GS40G - I210 PHY defines */
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#define GS40G_PAGE_SELECT 0x16
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#define GS40G_PAGE_SHIFT 16
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#define GS40G_OFFSET_MASK 0xFFFF
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#define GS40G_PAGE_2 0x20000
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#define GS40G_MAC_REG2 0x15
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#define GS40G_MAC_LB 0x4140
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#define GS40G_MAC_SPEED_1G 0X0006
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#define GS40G_COPPER_SPEC 0x0010
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#define GS40G_LINE_LB 0x4000
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/* SFP modules ID memory locations */
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#define E1000_SFF_IDENTIFIER_OFFSET 0x00
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#define E1000_SFF_IDENTIFIER_SFF 0x02
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