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perf vendor events: Add power8 PMU events 

Add mapfile.csv and power8.json files for the Power8 processor.

Changelog[v3]
	- [Namhyung Kim] Remove text from PublicDescription fields if it is
          identical to or prefix of BriefDescription.

Changelog[v2]
	- [Andi Kleen] Replace the vendor-family-model,version fields with
	  cpuid,version fields (to simplify mapfile)
	- Reuse the JSON files when possible (i.e multiple cpuids can refer
	  to the same JSON file) - so drop the 004d0100.json and use
	  power8.json in multiple entries in mapfile.
	- Add few more Power8 PVRs to mapfile

Changelog[v21]
	- Group events into per topic per cpu model.

Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
CC: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Link: http://lkml.kernel.org/n/tip-wr6rf3d3vvggy8180ftt2ro1@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
hifive-unleashed-5.1
Sukadev Bhattiprolu 2016-09-15 18:09:30 -04:00 committed by Arnaldo Carvalho de Melo
parent 1fbd54b2e2
commit 2a81fa3bb5
10 changed files with 6415 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
tools/perf/pmu-events/arch/powerpc/mapfile.csv 100644
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# Format:
# PVR,Version,JSON/file/pathname,Type
#
# where
# PVR Processor version
# Version could be used to track version of of JSON file
# but currently unused.
# JSON/file/pathname is the path to JSON file, relative
# to tools/perf/pmu-events/arch/powerpc/.
# Type is core, uncore etc
#
# Multiple PVRs could map to a single JSON file.
#
# Power8 entries
004b0000,1,power8.json,core
004c0000,1,power8.json,core
004d0000,1,power8.json,core
004d0100,1,power8.json,core
1 # Format:
2 # PVR,Version,JSON/file/pathname,Type
3 #
4 # where
5 # PVR Processor version
6 # Version could be used to track version of of JSON file
7 # but currently unused.
8 # JSON/file/pathname is the path to JSON file, relative
9 # to tools/perf/pmu-events/arch/powerpc/.
10 # Type is core, uncore etc
11 #
12 # Multiple PVRs could map to a single JSON file.
13 #
14 # Power8 entries
15 004b0000,1,power8.json,core
16 004c0000,1,power8.json,core
17 004d0000,1,power8.json,core
18 004d0100,1,power8.json,core

176
tools/perf/pmu-events/arch/powerpc/power8/cache.json 100644
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[
{,
"EventCode": "0x4c048",
"EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x3c048",
"EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x3c04c",
"EventName": "PM_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x1c042",
"EventName": "PM_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x200fe",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
"PublicDescription": ""
},
{,
"EventCode": "0x1c04e",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x3c040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x4c040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x1c040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x4c042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x300fe",
"EventName": "PM_DATA_FROM_L3MISS",
"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
"PublicDescription": ""
},
{,
"EventCode": "0x4c04e",
"EventName": "PM_DATA_FROM_L3MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x3c042",
"EventName": "PM_DATA_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x1c044",
"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x1c04c",
"EventName": "PM_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x4c04a",
"EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x1c048",
"EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c046",
"EventName": "PM_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x1c04a",
"EventName": "PM_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x3001a",
"EventName": "PM_DATA_TABLEWALK_CYC",
"BriefDescription": "Tablwalk Cycles (could be 1 or 2 active)",
"PublicDescription": "Data Tablewalk Active"
},
{,
"EventCode": "0x4e04e",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0xd094",
"EventName": "PM_DSLB_MISS",
"BriefDescription": "Data SLB Miss - Total of all segment sizes",
"PublicDescription": "Data SLB Miss - Total of all segment sizesData SLB misses"
},
{,
"EventCode": "0x1002c",
"EventName": "PM_L1_DCACHE_RELOADED_ALL",
"BriefDescription": "L1 data cache reloaded for demand or prefetch",
"PublicDescription": ""
},
{,
"EventCode": "0x300f6",
"EventName": "PM_L1_DCACHE_RELOAD_VALID",
"BriefDescription": "DL1 reloaded due to Demand Load",
"PublicDescription": ""
},
{,
"EventCode": "0x3e054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1",
"PublicDescription": ""
},
{,
"EventCode": "0x100ee",
"EventName": "PM_LD_REF_L1",
"BriefDescription": "All L1 D cache load references counted at finish, gated by reject",
"PublicDescription": "Load Ref count combined for all units"
},
{,
"EventCode": "0x300f0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1",
"PublicDescription": ""
},
]

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tools/perf/pmu-events/arch/powerpc/power8/floating-point.json 100644
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[
{,
"EventCode": "0x2000e",
"EventName": "PM_FXU_BUSY",
"BriefDescription": "fxu0 busy and fxu1 busy",
"PublicDescription": ""
},
{,
"EventCode": "0x1000e",
"EventName": "PM_FXU_IDLE",
"BriefDescription": "fxu0 idle and fxu1 idle",
"PublicDescription": ""
},
]

470
tools/perf/pmu-events/arch/powerpc/power8/frontend.json 100644
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[
{,
"EventCode": "0x2505e",
"EventName": "PM_BACK_BR_CMPL",
"BriefDescription": "Branch instruction completed with a target address less than current instruction address",
"PublicDescription": ""
},
{,
"EventCode": "0x10068",
"EventName": "PM_BRU_FIN",
"BriefDescription": "Branch Instruction Finished",
"PublicDescription": ""
},
{,
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "two path branch",
"PublicDescription": ""
},
{,
"EventCode": "0x40060",
"EventName": "PM_BR_CMPL",
"BriefDescription": "Branch Instruction completed",
"PublicDescription": ""
},
{,
"EventCode": "0x400f6",
"EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts",
"PublicDescription": ""
},
{,
"EventCode": "0x200fa",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken",
"PublicDescription": ""
},
{,
"EventCode": "0x10018",
"EventName": "PM_IC_DEMAND_CYC",
"BriefDescription": "Cycles when a demand ifetch was pending",
"PublicDescription": "Demand ifetch pending"
},
{,
"EventCode": "0x100f6",
"EventName": "PM_IERAT_RELOAD",
"BriefDescription": "Number of I-ERAT reloads",
"PublicDescription": "IERAT Reloaded (Miss)"
},
{,
"EventCode": "0x4006a",
"EventName": "PM_IERAT_RELOAD_16M",
"BriefDescription": "IERAT Reloaded (Miss) for a 16M page",
"PublicDescription": ""
},
{,
"EventCode": "0x20064",
"EventName": "PM_IERAT_RELOAD_4K",
"BriefDescription": "IERAT Miss (Not implemented as DI on POWER6)",
"PublicDescription": "IERAT Reloaded (Miss) for a 4k page"
},
{,
"EventCode": "0x3006a",
"EventName": "PM_IERAT_RELOAD_64K",
"BriefDescription": "IERAT Reloaded (Miss) for a 64k page",
"PublicDescription": ""
},
{,
"EventCode": "0x14050",
"EventName": "PM_INST_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
},
{,
"EventCode": "0x2",
"EventName": "PM_INST_CMPL",
"BriefDescription": "Number of PowerPC Instructions that completed",
"PublicDescription": "PPC Instructions Finished (completed)"
},
{,
"EventCode": "0x200f2",
"EventName": "PM_INST_DISP",
"BriefDescription": "PPC Dispatched",
"PublicDescription": ""
},
{,
"EventCode": "0x44048",
"EventName": "PM_INST_FROM_DL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x34048",
"EventName": "PM_INST_FROM_DL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x3404c",
"EventName": "PM_INST_FROM_DL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x4404c",
"EventName": "PM_INST_FROM_DMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x14042",
"EventName": "PM_INST_FROM_L2",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x1404e",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x34040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x44040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x24040",
"EventName": "PM_INST_FROM_L2_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x14040",
"EventName": "PM_INST_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x300fa",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
"PublicDescription": "Inst from L3 miss"
},
{,
"EventCode": "0x4404e",
"EventName": "PM_INST_FROM_L3MISS_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to a instruction fetch",
"PublicDescription": "The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x1404c",
"EventName": "PM_INST_FROM_LL4",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x24048",
"EventName": "PM_INST_FROM_LMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x2404c",
"EventName": "PM_INST_FROM_MEMORY",
"BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x4404a",
"EventName": "PM_INST_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x1404a",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x2404a",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x3404a",
"EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1"
},
{,
"EventCode": "0x24050",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch"
},
{,
"EventCode": "0x24052",
"EventName": "PM_INST_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
},
{,
"EventCode": "0x14052",
"EventName": "PM_INST_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch"
},
{,
"EventCode": "0x1003a",
"EventName": "PM_INST_IMC_MATCH_CMPL",
"BriefDescription": "IMC Match Count ( Not architected in P8)",
"PublicDescription": ""
},
{,
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
"PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor an instruction fetch"
},
{,
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch",
"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor an instruction fetch"
},
{,
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch"
},
{,
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
},
{,
"EventCode": "0x44050",
"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch"
},
{,
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x35048",
"EventName": "PM_IPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3504c",
"EventName": "PM_IPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4504c",
"EventName": "PM_IPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x15042",
"EventName": "PM_IPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1504e",
"EventName": "PM_IPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x25040",
"EventName": "PM_IPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x15040",
"EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x45042",
"EventName": "PM_IPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4504e",
"EventName": "PM_IPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x35042",
"EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1504c",
"EventName": "PM_IPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x25048",
"EventName": "PM_IPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2504c",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4504a",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1504a",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2504a",
"EventName": "PM_IPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3504a",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
},
{,
"EventCode": "0xd096",
"EventName": "PM_ISLB_MISS",
"BriefDescription": "I SLB Miss",
"PublicDescription": ""
},
{,
"EventCode": "0x400fc",
"EventName": "PM_ITLB_MISS",
"BriefDescription": "ITLB Reloaded (always zero on POWER6)",
"PublicDescription": ""
},
{,
"EventCode": "0x200fd",
"EventName": "PM_L1_ICACHE_MISS",
"BriefDescription": "Demand iCache Miss",
"PublicDescription": ""
},
{,
"EventCode": "0x40012",
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
"BriefDescription": "Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch",
"PublicDescription": ""
},
{,
"EventCode": "0x30068",
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
"BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
"PublicDescription": ""
},
{,
"EventCode": "0x300f4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished when both threads in run_cycles",
"PublicDescription": "Concurrent Run Instructions"
},
{,
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Instructions completed in transactional state",
"PublicDescription": ""
},
{,
"EventCode": "0x4e014",
"EventName": "PM_TM_TX_PASS_RUN_INST",
"BriefDescription": "run instructions spent in successful transactions",
"PublicDescription": ""
},
]

794
tools/perf/pmu-events/arch/powerpc/power8/marked.json 100644
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@ -0,0 +1,794 @@
[
{,
"EventCode": "0x3515e",
"EventName": "PM_MRK_BACK_BR_CMPL",
"BriefDescription": "Marked branch instruction completed with a target address less than current instruction address",
"PublicDescription": ""
},
{,
"EventCode": "0x2013a",
"EventName": "PM_MRK_BRU_FIN",
"BriefDescription": "bru marked instr finish",
"PublicDescription": ""
},
{,
"EventCode": "0x1016e",
"EventName": "PM_MRK_BR_CMPL",
"BriefDescription": "Branch Instruction completed",
"PublicDescription": ""
},
{,
"EventCode": "0x301e4",
"EventName": "PM_MRK_BR_MPRED_CMPL",
"BriefDescription": "Marked Branch Mispredicted",
"PublicDescription": ""
},
{,
"EventCode": "0x101e2",
"EventName": "PM_MRK_BR_TAKEN_CMPL",
"BriefDescription": "Marked Branch Taken completed",
"PublicDescription": ""
},
{,
"EventCode": "0x4d148",
"EventName": "PM_MRK_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3d148",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2c128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3d14c",
"EventName": "PM_MRK_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2c12c",
"EventName": "PM_MRK_DATA_FROM_DL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d14c",
"EventName": "PM_MRK_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d12c",
"EventName": "PM_MRK_DATA_FROM_DMEM_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d142",
"EventName": "PM_MRK_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d14e",
"EventName": "PM_MRK_DATA_FROM_L2MISS",
"BriefDescription": "Data cache reload L2 miss",
"PublicDescription": ""
},
{,
"EventCode": "0x4c12e",
"EventName": "PM_MRK_DATA_FROM_L2MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c122",
"EventName": "PM_MRK_DATA_FROM_L2_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3d140",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2c120",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d140",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d120",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d140",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d120",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d140",
"EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c120",
"EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d142",
"EventName": "PM_MRK_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x201e4",
"EventName": "PM_MRK_DATA_FROM_L3MISS",
"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d12e",
"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d122",
"EventName": "PM_MRK_DATA_FROM_L3_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3d142",
"EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2c122",
"EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d142",
"EventName": "PM_MRK_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d122",
"EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d144",
"EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c124",
"EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d14c",
"EventName": "PM_MRK_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c12c",
"EventName": "PM_MRK_DATA_FROM_LL4_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d148",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d14c",
"EventName": "PM_MRK_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d12c",
"EventName": "PM_MRK_DATA_FROM_MEMORY_CYC",
"BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d14a",
"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d12a",
"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d148",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c128",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d146",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d126",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x1d14a",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c12a",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2d14a",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x4d12a",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x3d14a",
"EventName": "PM_MRK_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x2c12a",
"EventName": "PM_MRK_DATA_FROM_RMEM_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
},
{,
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event",
"PublicDescription": ""
},
{,
"EventCode": "0x301e6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes",
"PublicDescription": ""
},
{,
"EventCode": "0x4d154",
"EventName": "PM_MRK_DERAT_MISS_16G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x3d154",
"EventName": "PM_MRK_DERAT_MISS_16M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M",
"PublicDescription": ""
},
{,
"EventCode": "0x1d156",
"EventName": "PM_MRK_DERAT_MISS_4K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K",
"PublicDescription": ""
},
{,
"EventCode": "0x2d154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
},
{,
"EventCode": "0x20132",
"EventName": "PM_MRK_DFU_FIN",
"BriefDescription": "Decimal Unit marked Instruction Finish",
"PublicDescription": ""
},
{,
"EventCode": "0x4f148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3f148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3f14c",
"EventName": "PM_MRK_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4f14c",
"EventName": "PM_MRK_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f142",
"EventName": "PM_MRK_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f14e",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2f140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f140",
"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4f142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4f14e",
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3f142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2f142",
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f144",
"EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f14c",
"EventName": "PM_MRK_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2f148",
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2f14c",
"EventName": "PM_MRK_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4f14a",
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f148",
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2f146",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1f14a",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2f14a",
"EventName": "PM_MRK_DPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3f14a",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x401e4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss",
"PublicDescription": ""
},
{,
"EventCode": "0x1d158",
"EventName": "PM_MRK_DTLB_MISS_16G",
"BriefDescription": "Marked Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x4d156",
"EventName": "PM_MRK_DTLB_MISS_16M",
"BriefDescription": "Marked Data TLB Miss page size 16M",
"PublicDescription": ""
},
{,
"EventCode": "0x2d156",
"EventName": "PM_MRK_DTLB_MISS_4K",
"BriefDescription": "Marked Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
"EventCode": "0x3d156",
"EventName": "PM_MRK_DTLB_MISS_64K",
"BriefDescription": "Marked Data TLB Miss page size 64K",
"PublicDescription": ""
},
{,
"EventCode": "0x40154",
"EventName": "PM_MRK_FAB_RSP_BKILL",
"BriefDescription": "Marked store had to do a bkill",
"PublicDescription": ""
},
{,
"EventCode": "0x2f150",
"EventName": "PM_MRK_FAB_RSP_BKILL_CYC",
"BriefDescription": "cycles L2 RC took for a bkill",
"PublicDescription": ""
},
{,
"EventCode": "0x3015e",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
},
{,
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim",
"PublicDescription": ""
},
{,
"EventCode": "0x2f152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim",
"PublicDescription": ""
},
{,
"EventCode": "0x4015e",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count",
"PublicDescription": ""
},
{,
"EventCode": "0x1015e",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention",
"PublicDescription": ""
},
{,
"EventCode": "0x4f150",
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
"BriefDescription": "cycles L2 RC took for a rwitm",
"PublicDescription": ""
},
{,
"EventCode": "0x2015e",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
},
{,
"EventCode": "0x20134",
"EventName": "PM_MRK_FXU_FIN",
"BriefDescription": "fxu marked instr finish",
"PublicDescription": ""
},
{,
"EventCode": "0x401e0",
"EventName": "PM_MRK_INST_CMPL",
"BriefDescription": "marked instruction completed",
"PublicDescription": ""
},
{,
"EventCode": "0x20130",
"EventName": "PM_MRK_INST_DECODED",
"BriefDescription": "marked instruction decoded",
"PublicDescription": "marked instruction decoded. Name from ISU?"
},
{,
"EventCode": "0x101e0",
"EventName": "PM_MRK_INST_DISP",
"BriefDescription": "The thread has dispatched a randomly sampled marked instruction",
"PublicDescription": "Marked Instruction dispatched"
},
{,
"EventCode": "0x30130",
"EventName": "PM_MRK_INST_FIN",
"BriefDescription": "marked instruction finished",
"PublicDescription": "marked instr finish any unit"
},
{,
"EventCode": "0x401e6",
"EventName": "PM_MRK_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
"PublicDescription": "n/a"
},
{,
"EventCode": "0x10132",
"EventName": "PM_MRK_INST_ISSUED",
"BriefDescription": "Marked instruction issued",
"PublicDescription": ""
},
{,
"EventCode": "0x40134",
"EventName": "PM_MRK_INST_TIMEO",
"BriefDescription": "marked Instruction finish timeout (instruction lost)",
"PublicDescription": ""
},
{,
"EventCode": "0x101e4",
"EventName": "PM_MRK_L1_ICACHE_MISS",
"BriefDescription": "sampled Instruction suffered an icache Miss",
"PublicDescription": "Marked L1 Icache Miss"
},
{,
"EventCode": "0x101ea",
"EventName": "PM_MRK_L1_RELOAD_VALID",
"BriefDescription": "Marked demand reload",
"PublicDescription": ""
},
{,
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2",
"PublicDescription": ""
},
{,
"EventCode": "0x3012a",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done",
"PublicDescription": ""
},
{,
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
},
{,
"EventCode": "0x1013e",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss cycles",
"PublicDescription": "Marked Load exposed Miss (use edge detect to count #)"
},
{,
"EventCode": "0x201e2",
"EventName": "PM_MRK_LD_MISS_L1",
"BriefDescription": "Marked DL1 Demand Miss counted at exec time",
"PublicDescription": ""
},
{,
"EventCode": "0x4013e",
"EventName": "PM_MRK_LD_MISS_L1_CYC",
"BriefDescription": "Marked ld latency",
"PublicDescription": ""
},
{,
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr finish",
"PublicDescription": ""
},
{,
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished",
"PublicDescription": ""
},
{,
"EventCode": "0x1d15e",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Marked run cycles",
"PublicDescription": ""
},
{,
"EventCode": "0x3013e",
"EventName": "PM_MRK_STALL_CMPLU_CYC",
"BriefDescription": "Marked Group completion Stall",
"PublicDescription": "Marked Group Completion Stall cycles (use edge detect to count #)"
},
{,
"EventCode": "0x3e158",
"EventName": "PM_MRK_STCX_FAIL",
"BriefDescription": "marked stcx failed",
"PublicDescription": ""
},
{,
"EventCode": "0x10134",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "marked store completed and sent to nest",
"PublicDescription": "Marked store completed"
},
{,
"EventCode": "0x30134",
"EventName": "PM_MRK_ST_CMPL_INT",
"BriefDescription": "marked store finished with intervention",
"PublicDescription": "marked store complete (data home) with intervention"
},
{,
"EventCode": "0x3f150",
"EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
"BriefDescription": "cycles to drain st from core to L2",
"PublicDescription": ""
},
{,
"EventCode": "0x3012c",
"EventName": "PM_MRK_ST_FWD",
"BriefDescription": "Marked st forwards",
"PublicDescription": ""
},
{,
"EventCode": "0x1f150",
"EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
"BriefDescription": "cycles from L2 rc disp to l2 rc completion",
"PublicDescription": ""
},
{,
"EventCode": "0x20138",
"EventName": "PM_MRK_ST_NEST",
"BriefDescription": "Marked store sent to nest",
"PublicDescription": ""
},
{,
"EventCode": "0x30132",
"EventName": "PM_MRK_VSU_FIN",
"BriefDescription": "VSU marked instr finish",
"PublicDescription": "vsu (fpu) marked instr finish"
},
{,
"EventCode": "0x3d15e",
"EventName": "PM_MULT_MRK",
"BriefDescription": "mult marked instr",
"PublicDescription": ""
},
{,
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x1515c",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x15156",
"EventName": "PM_SYNC_MRK_FX_DIVIDE",
"BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x1515a",
"EventName": "PM_SYNC_MRK_L2MISS",
"BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x15154",
"EventName": "PM_SYNC_MRK_L3MISS",
"BriefDescription": "Marked L3 misses that can throw a synchronous interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x15150",
"EventName": "PM_SYNC_MRK_PROBE_NOP",
"BriefDescription": "Marked probeNops which can cause synchronous interrupts",
"PublicDescription": ""
},
]

212
tools/perf/pmu-events/arch/powerpc/power8/memory.json 100644
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@ -0,0 +1,212 @@
[
{,
"EventCode": "0x10050",
"EventName": "PM_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d)"
},
{,
"EventCode": "0x1c050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load"
},
{,
"EventCode": "0x4c04c",
"EventName": "PM_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c048",
"EventName": "PM_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c04c",
"EventName": "PM_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c04a",
"EventName": "PM_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x3c04a",
"EventName": "PM_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1"
},
{,
"EventCode": "0x2c050",
"EventName": "PM_DATA_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load"
},
{,
"EventCode": "0x2c052",
"EventName": "PM_DATA_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
},
{,
"EventCode": "0x1c052",
"EventName": "PM_DATA_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load"
},
{,
"EventCode": "0x1c054",
"EventName": "PM_DATA_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x4c052",
"EventName": "PM_DATA_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load",
"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor a demand load"
},
{,
"EventCode": "0x3c050",
"EventName": "PM_DATA_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load"
},
{,
"EventCode": "0x3c052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
},
{,
"EventCode": "0x4c050",
"EventName": "PM_DATA_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load"
},
{,
"EventCode": "0x3e04c",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4e04c",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3e04a",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x20050",
"EventName": "PM_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
},
{,
"EventCode": "0x20052",
"EventName": "PM_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro"
},
{,
"EventCode": "0x10052",
"EventName": "PM_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(Group) to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x18082",
"EventName": "PM_L3_CO_MEPF",
"BriefDescription": "L3 CO of line in Mep state ( includes casthrough",
"PublicDescription": ""
},
{,
"EventCode": "0x4c058",
"EventName": "PM_MEM_CO",
"BriefDescription": "Memory castouts from this lpar",
"PublicDescription": ""
},
{,
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control",
"PublicDescription": ""
},
{,
"EventCode": "0x40056",
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium",
"PublicDescription": ""
},
{,
"EventCode": "0x1c05e",
"EventName": "PM_MEM_LOC_THRESH_LSU_MED",
"BriefDescription": "Local memory above theshold for data prefetch",
"PublicDescription": ""
},
{,
"EventCode": "0x2c058",
"EventName": "PM_MEM_PREF",
"BriefDescription": "Memory prefetch for this lpar. Includes L4",
"PublicDescription": ""
},
{,
"EventCode": "0x10056",
"EventName": "PM_MEM_READ",
"BriefDescription": "Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
"PublicDescription": ""
},
{,
"EventCode": "0x3c05e",
"EventName": "PM_MEM_RWITM",
"BriefDescription": "Memory rwitm for this lpar",
"PublicDescription": ""
},
{,
"EventCode": "0x3006e",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles",
"PublicDescription": "Nest reference clocks"
},
{,
"EventCode": "0x10054",
"EventName": "PM_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x40052",
"EventName": "PM_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x30050",
"EventName": "PM_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x30052",
"EventName": "PM_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or"
},
{,
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": "Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
]

4064
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tools/perf/pmu-events/arch/powerpc/power8/pipeline.json 100644
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[
{,
"EventCode": "0x100f2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished",
"PublicDescription": "1 or more ppc insts finished (completed)"
},
{,
"EventCode": "0x400f2",
"EventName": "PM_1PLUS_PPC_DISP",
"BriefDescription": "Cycles at least one Instr Dispatched",
"PublicDescription": "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521"
},
{,
"EventCode": "0x100fa",
"EventName": "PM_ANY_THRD_RUN_CYC",
"BriefDescription": "One of threads in run_cycles",
"PublicDescription": "Any thread in run_cycles (was one thread in run_cycles)"
},
{,
"EventCode": "0x4000a",
"EventName": "PM_CMPLU_STALL",
"BriefDescription": "Completion stall",
"PublicDescription": ""
},
{,
"EventCode": "0x4d018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit",
"PublicDescription": ""
},
{,
"EventCode": "0x2c012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Completion stall by Dcache miss",
"PublicDescription": ""
},
{,
"EventCode": "0x2c018",
"EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
"PublicDescription": ""
},
{,
"EventCode": "0x2c016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
"PublicDescription": ""
},
{,
"EventCode": "0x4c016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
"PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict"
},
{,
"EventCode": "0x4c01a",
"EventName": "PM_CMPLU_STALL_DMISS_L3MISS",
"BriefDescription": "Completion stall due to cache miss resolving missed the L3",
"PublicDescription": ""
},
{,
"EventCode": "0x4c018",
"EventName": "PM_CMPLU_STALL_DMISS_LMEM",
"BriefDescription": "Completion stall due to cache miss that resolves in local memory",
"PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory"
},
{,
"EventCode": "0x2c01c",
"EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
"PublicDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"
},
{,
"EventCode": "0x4c012",
"EventName": "PM_CMPLU_STALL_ERAT_MISS",
"BriefDescription": "Completion stall due to LSU reject ERAT miss",
"PublicDescription": ""
},
{,
"EventCode": "0x4d016",
"EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency fixed point instruction",
"PublicDescription": ""
},
{,
"EventCode": "0x2d016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Completion stall due to FXU",
"PublicDescription": ""
},
{,
"EventCode": "0x30036",
"EventName": "PM_CMPLU_STALL_HWSYNC",
"BriefDescription": "completion stall due to hwsync",
"PublicDescription": ""
},
{,
"EventCode": "0x4d014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Completion stall due to a Load finish",
"PublicDescription": ""
},
{,
"EventCode": "0x2c010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction",
"PublicDescription": ""
},
{,
"EventCode": "0x10036",
"EventName": "PM_CMPLU_STALL_LWSYNC",
"BriefDescription": "completion stall due to isync/lwsync",
"PublicDescription": ""
},
{,
"EventCode": "0x30006",
"EventName": "PM_CMPLU_STALL_OTHER_CMPL",
"BriefDescription": "Instructions core completed while this tread was stalled",
"PublicDescription": "Instructions core completed while this thread was stalled"
},
{,
"EventCode": "0x4c01c",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward",
"PublicDescription": ""
},
{,
"EventCode": "0x1001c",
"EventName": "PM_CMPLU_STALL_THRD",
"BriefDescription": "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
"PublicDescription": "Completion stall due to thread conflict"
},
{,
"EventCode": "0x1e",
"EventName": "PM_CYC",
"BriefDescription": "Cycles",
"PublicDescription": ""
},
{,
"EventCode": "0x10006",
"EventName": "PM_DISP_HELD",
"BriefDescription": "Dispatch Held",
"PublicDescription": ""
},
{,
"EventCode": "0x4003c",
"EventName": "PM_DISP_HELD_SYNC_HOLD",
"BriefDescription": "Dispatch held due to SYNC hold",
"PublicDescription": ""
},
{,
"EventCode": "0x200f8",
"EventName": "PM_EXT_INT",
"BriefDescription": "external interrupt",
"PublicDescription": ""
},
{,
"EventCode": "0x400f8",
"EventName": "PM_FLUSH",
"BriefDescription": "Flush (any type)",
"PublicDescription": ""
},
{,
"EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "Completion Flush",
"PublicDescription": ""
},
{,
"EventCode": "0x3000c",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B",
"PublicDescription": "Frequency is being slewed down due to Power Management"
},
{,
"EventCode": "0x4000c",
"EventName": "PM_FREQ_UP",
"BriefDescription": "Power Management: Above Threshold A",
"PublicDescription": "Frequency is being slewed up due to Power Management"
},
{,
"EventCode": "0x2000a",
"EventName": "PM_HV_CYC",
"BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
"PublicDescription": "cycles in hypervisor mode"
},
{,
"EventCode": "0x3405e",
"EventName": "PM_IFETCH_THROTTLE",
"BriefDescription": "Cycles in which Instruction fetch throttle was active",
"PublicDescription": "Cycles instruction fecth was throttled in IFU"
},
{,
"EventCode": "0x10014",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed",
"PublicDescription": "IOPS Completed"
},
{,
"EventCode": "0x3c058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
},
{,
"EventCode": "0x1002e",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed",
"PublicDescription": ""
},
{,
"EventCode": "0x10062",
"EventName": "PM_LD_L3MISS_PEND_CYC",
"BriefDescription": "Cycles L3 miss was pending for this thread",
"PublicDescription": ""
},
{,
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished an instruction (up to 2 per cycle)",
"PublicDescription": ""
},
{,
"EventCode": "0x2003e",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "LSU empty (lmq and srq empty)",
"PublicDescription": ""
},
{,
"EventCode": "0x2e05c",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
"PublicDescription": ""
},
{,
"EventCode": "0x4e05c",
"EventName": "PM_LSU_REJECT_LHS",
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
"PublicDescription": ""
},
{,
"EventCode": "0x1e05c",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU reject due to LMQ full ( 4 per cycle)",
"PublicDescription": ""
},
{,
"EventCode": "0x1001a",
"EventName": "PM_LSU_SRQ_FULL_CYC",
"BriefDescription": "Storage Queue is full and is blocking dispatch",
"PublicDescription": "SRQ is Full"
},
{,
"EventCode": "0x40014",
"EventName": "PM_PROBE_NOP_DISP",
"BriefDescription": "ProbeNops dispatched",
"PublicDescription": ""
},
{,
"EventCode": "0x600f4",
"EventName": "PM_RUN_CYC",
"BriefDescription": "Run_cycles",
"PublicDescription": ""
},
{,
"EventCode": "0x3006c",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
"PublicDescription": ""
},
{,
"EventCode": "0x2006c",
"EventName": "PM_RUN_CYC_SMT4_MODE",
"BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
"PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
},
{,
"EventCode": "0x1006c",
"EventName": "PM_RUN_CYC_ST_MODE",
"BriefDescription": "Cycles run latch is set and core is in ST mode",
"PublicDescription": ""
},
{,
"EventCode": "0x500fa",
"EventName": "PM_RUN_INST_CMPL",
"BriefDescription": "Run_Instructions",
"PublicDescription": ""
},
{,
"EventCode": "0x1e058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed",
"PublicDescription": ""
},
{,
"EventCode": "0x20016",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Store completion count",
"PublicDescription": ""
},
{,
"EventCode": "0x200f0",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store Instructions Finished",
"PublicDescription": "Store Instructions Finished (store sent to nest)"
},
{,
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished",
"PublicDescription": ""
},
{,
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when a tablewalk (I or D) is active",
"PublicDescription": "Tablewalk Active"
},
{,
"EventCode": "0x300f8",
"EventName": "PM_TB_BIT_TRANS",
"BriefDescription": "timebase event",
"PublicDescription": ""
},
{,
"EventCode": "0x2000c",
"EventName": "PM_THRD_ALL_RUN_CYC",
"BriefDescription": "All Threads in Run_cycles (was both threads in run_cycles)",
"PublicDescription": ""
},
{,
"EventCode": "0x30058",
"EventName": "PM_TLBIE_FIN",
"BriefDescription": "tlbie finished",
"PublicDescription": ""
},
{,
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state",
"PublicDescription": ""
},
{,
"EventCode": "0x2e012",
"EventName": "PM_TM_TX_PASS_RUN_CYC",
"BriefDescription": "cycles spent in successful transactions",
"PublicDescription": "run cycles spent in successful transactions"
},
]

140
tools/perf/pmu-events/arch/powerpc/power8/pmc.json 100644
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[
{,
"EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1",
"PublicDescription": ""
},
{,
"EventCode": "0x30010",
"EventName": "PM_PMC2_OVERFLOW",
"BriefDescription": "Overflow from counter 2",
"PublicDescription": ""
},
{,
"EventCode": "0x30020",
"EventName": "PM_PMC2_REWIND",
"BriefDescription": "PMC2 Rewind Event (did not match condition)",
"PublicDescription": ""
},
{,
"EventCode": "0x10022",
"EventName": "PM_PMC2_SAVED",
"BriefDescription": "PMC2 Rewind Value saved",
"PublicDescription": "PMC2 Rewind Value saved (matched condition)"
},
{,
"EventCode": "0x40010",
"EventName": "PM_PMC3_OVERFLOW",
"BriefDescription": "Overflow from counter 3",
"PublicDescription": ""
},
{,
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4",
"PublicDescription": ""
},
{,
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event",
"PublicDescription": "PMC4 Rewind Event (did not match condition)"
},
{,
"EventCode": "0x30022",
"EventName": "PM_PMC4_SAVED",
"BriefDescription": "PMC4 Rewind Value saved (matched condition)",
"PublicDescription": ""
},
{,
"EventCode": "0x10024",
"EventName": "PM_PMC5_OVERFLOW",
"BriefDescription": "Overflow from counter 5",
"PublicDescription": ""
},
{,
"EventCode": "0x30024",
"EventName": "PM_PMC6_OVERFLOW",
"BriefDescription": "Overflow from counter 6",
"PublicDescription": ""
},
{,
"EventCode": "0x400f4",
"EventName": "PM_RUN_PURR",
"BriefDescription": "Run_PURR",
"PublicDescription": ""
},
{,
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR",
"PublicDescription": ""
},
{,
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF",
"PublicDescription": ""
},
{,
"EventCode": "0x301ea",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024",
"PublicDescription": ""
},
{,
"EventCode": "0x401ea",
"EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128",
"PublicDescription": ""
},
{,
"EventCode": "0x401ec",
"EventName": "PM_THRESH_EXC_2048",
"BriefDescription": "Threshold counter exceeded a value of 2048",
"PublicDescription": ""
},
{,
"EventCode": "0x101e8",
"EventName": "PM_THRESH_EXC_256",
"BriefDescription": "Threshold counter exceed a count of 256",
"PublicDescription": ""
},
{,
"EventCode": "0x201e6",
"EventName": "PM_THRESH_EXC_32",
"BriefDescription": "Threshold counter exceeded a value of 32",
"PublicDescription": ""
},
{,
"EventCode": "0x101e6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096",
"PublicDescription": ""
},
{,
"EventCode": "0x201e8",
"EventName": "PM_THRESH_EXC_512",
"BriefDescription": "Threshold counter exceeded a value of 512",
"PublicDescription": ""
},
{,
"EventCode": "0x301e8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "IFU non-branch finished",
"PublicDescription": "Threshold counter exceeded a value of 64"
},
{,
"EventCode": "0x101ec",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded",
"PublicDescription": ""
},
{,
"EventCode": "0x4016e",
"EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold",
"PublicDescription": ""
},
]

176
tools/perf/pmu-events/arch/powerpc/power8/translation.json 100644
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@ -0,0 +1,176 @@
[
{,
"EventCode": "0x4c054",
"EventName": "PM_DERAT_MISS_16G",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x3c054",
"EventName": "PM_DERAT_MISS_16M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
"PublicDescription": ""
},
{,
"EventCode": "0x1c056",
"EventName": "PM_DERAT_MISS_4K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
"PublicDescription": ""
},
{,
"EventCode": "0x2c054",
"EventName": "PM_DERAT_MISS_64K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
},
{,
"EventCode": "0x4e048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3e048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e042",
"EventName": "PM_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e04e",
"EventName": "PM_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2e040",
"EventName": "PM_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e040",
"EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4e042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x3e042",
"EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2e042",
"EventName": "PM_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e044",
"EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e04c",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2e048",
"EventName": "PM_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2e04c",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x4e04a",
"EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e048",
"EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2e046",
"EventName": "PM_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x1e04a",
"EventName": "PM_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x2e04a",
"EventName": "PM_DPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request",
"PublicDescription": ""
},
{,
"EventCode": "0x300fc",
"EventName": "PM_DTLB_MISS",
"BriefDescription": "Data PTEG reload",
"PublicDescription": "Data PTEG Reloaded (DTLB Miss)"
},
{,
"EventCode": "0x1c058",
"EventName": "PM_DTLB_MISS_16G",
"BriefDescription": "Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x4c056",
"EventName": "PM_DTLB_MISS_16M",
"BriefDescription": "Data TLB Miss page size 16M",
"PublicDescription": ""
},
{,
"EventCode": "0x2c056",
"EventName": "PM_DTLB_MISS_4K",
"BriefDescription": "Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
"EventCode": "0x3c056",
"EventName": "PM_DTLB_MISS_64K",
"BriefDescription": "Data TLB Miss page size 64K",
"PublicDescription": ""
},
{,
"EventCode": "0x200f6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss",
"PublicDescription": "DERAT Reloaded (Miss)"
},
{,
"EventCode": "0x20066",
"EventName": "PM_TLB_MISS",
"BriefDescription": "TLB Miss (I + D)",
"PublicDescription": ""
},
]