drm/gma500/cdv: Make use of the generic clock code
Add chip specific callbacks for the generic and non-generic clock calculation code. Also remove as much dupilicated code as possible. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>hifive-unleashed-5.1
Patrik Jakobsson
parent
5ea75e0f05
commit
2adb29ff61
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@ -641,6 +641,7 @@ const struct psb_ops cdv_chip_ops = {
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.crtc_helper = &cdv_intel_helper_funcs,
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.crtc_funcs = &cdv_intel_crtc_funcs,
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.clock_funcs = &cdv_clock_funcs,
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.output_init = cdv_output_init,
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.hotplug = cdv_hotplug_event,
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@ -17,6 +17,7 @@
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extern const struct drm_crtc_helper_funcs cdv_intel_helper_funcs;
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extern const struct drm_crtc_funcs cdv_intel_crtc_funcs;
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extern const struct gma_clock_funcs cdv_clock_funcs;
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extern void cdv_intel_crt_init(struct drm_device *dev,
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struct psb_intel_mode_device *mode_dev);
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extern void cdv_intel_lvds_init(struct drm_device *dev,
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@ -30,43 +30,10 @@
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#include "power.h"
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#include "cdv_device.h"
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static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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struct drm_crtc *crtc, int target,
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int refclk, struct gma_clock_t *best_clock);
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struct cdv_intel_range_t {
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int min, max;
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};
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struct cdv_intel_p2_t {
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int dot_limit;
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int p2_slow, p2_fast;
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};
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struct cdv_intel_clock_t {
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/* given values */
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int n;
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int m1, m2;
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int p1, p2;
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/* derived values */
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int dot;
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int vco;
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int m;
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int p;
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};
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#define INTEL_P2_NUM 2
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struct cdv_intel_limit_t {
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struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
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struct cdv_intel_p2_t p2;
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bool (*find_pll)(const struct cdv_intel_limit_t *, struct drm_crtc *,
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int, int, struct cdv_intel_clock_t *);
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};
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static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit,
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struct drm_crtc *crtc, int target, int refclk,
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struct cdv_intel_clock_t *best_clock);
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static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target,
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int refclk,
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struct cdv_intel_clock_t *best_clock);
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#define CDV_LIMIT_SINGLE_LVDS_96 0
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#define CDV_LIMIT_SINGLE_LVDS_100 1
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@ -75,7 +42,7 @@ static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct
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#define CDV_LIMIT_DP_27 4
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#define CDV_LIMIT_DP_100 5
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static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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static const struct gma_limit_t cdv_intel_limits[] = {
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{ /* CDV_SINGLE_LVDS_96MHz */
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.dot = {.min = 20000, .max = 115500},
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.vco = {.min = 1800000, .max = 3600000},
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@ -85,9 +52,8 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 28, .max = 140},
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.p1 = {.min = 2, .max = 10},
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.p2 = {.dot_limit = 200000,
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.p2_slow = 14, .p2_fast = 14},
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.find_pll = cdv_intel_find_best_PLL,
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.p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_SINGLE_LVDS_100MHz */
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.dot = {.min = 20000, .max = 115500},
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@ -102,7 +68,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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* is 80-224Mhz. Prefer single channel as much as possible.
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*/
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.p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
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.find_pll = cdv_intel_find_best_PLL,
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_DAC_HDMI_27MHz */
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.dot = {.min = 20000, .max = 400000},
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@ -114,7 +80,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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.p = {.min = 5, .max = 90},
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.p1 = {.min = 1, .max = 9},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = cdv_intel_find_best_PLL,
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_DAC_HDMI_96MHz */
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.dot = {.min = 20000, .max = 400000},
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@ -126,7 +92,7 @@ static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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.p = {.min = 5, .max = 100},
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.p1 = {.min = 1, .max = 10},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = cdv_intel_find_best_PLL,
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.find_pll = gma_find_best_pll,
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},
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{ /* CDV_DP_27MHz */
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.dot = {.min = 160000, .max = 272000},
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@ -255,7 +221,7 @@ void cdv_sb_reset(struct drm_device *dev)
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*/
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static int
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cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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struct cdv_intel_clock_t *clock, bool is_lvds, u32 ddi_select)
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struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
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{
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struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_crtc->pipe;
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@ -405,31 +371,11 @@ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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return 0;
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}
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/*
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* Returns whether any encoder on the specified pipe is of the specified type
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*/
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static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
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static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
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int refclk)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *l_entry;
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list_for_each_entry(l_entry, &mode_config->connector_list, head) {
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if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
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struct psb_intel_encoder *psb_intel_encoder =
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psb_intel_attached_encoder(l_entry);
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if (psb_intel_encoder->type == type)
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return true;
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}
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}
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return false;
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}
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static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
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int refclk)
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{
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const struct cdv_intel_limit_t *limit;
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if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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const struct gma_limit_t *limit;
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if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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/*
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* Now only single-channel LVDS is supported on CDV. If it is
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* incorrect, please add the dual-channel LVDS.
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@ -454,8 +400,7 @@ static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
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}
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/* m1 is reserved as 0 in CDV, n is a ring counter */
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static void cdv_intel_clock(struct drm_device *dev,
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int refclk, struct cdv_intel_clock_t *clock)
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static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
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{
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clock->m = clock->m2 + 2;
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clock->p = clock->p1 * clock->p2;
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@ -463,93 +408,12 @@ static void cdv_intel_clock(struct drm_device *dev,
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clock->dot = clock->vco / clock->p;
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}
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#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
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static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
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const struct cdv_intel_limit_t *limit,
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struct cdv_intel_clock_t *clock)
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static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
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struct drm_crtc *crtc, int target,
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int refclk,
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struct gma_clock_t *best_clock)
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{
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if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
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INTELPllInvalid("p1 out of range\n");
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if (clock->p < limit->p.min || limit->p.max < clock->p)
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INTELPllInvalid("p out of range\n");
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/* unnecessary to check the range of m(m1/M2)/n again */
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if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
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INTELPllInvalid("vco out of range\n");
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/* XXX: We may need to be checking "Dot clock"
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* depending on the multiplier, connector, etc.,
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* rather than just a single range.
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*/
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if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
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INTELPllInvalid("dot out of range\n");
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return true;
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}
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static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit,
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struct drm_crtc *crtc, int target, int refclk,
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struct cdv_intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct cdv_intel_clock_t clock;
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int err = target;
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if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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(REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
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/*
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* For LVDS, if the panel is on, just rely on its current
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* settings for dual-channel. We haven't figured out how to
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* reliably set up different single/dual channel state, if we
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* even can.
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*/
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if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
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LVDS_CLKB_POWER_UP)
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clock.p2 = limit->p2.p2_fast;
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else
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clock.p2 = limit->p2.p2_slow;
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} else {
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if (target < limit->p2.dot_limit)
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clock.p2 = limit->p2.p2_slow;
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else
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clock.p2 = limit->p2.p2_fast;
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}
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memset(best_clock, 0, sizeof(*best_clock));
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clock.m1 = 0;
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/* m1 is reserved as 0 in CDV, n is a ring counter.
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So skip the m1 loop */
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for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
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for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
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clock.m2++) {
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for (clock.p1 = limit->p1.min;
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clock.p1 <= limit->p1.max;
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clock.p1++) {
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int this_err;
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cdv_intel_clock(dev, refclk, &clock);
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if (!cdv_intel_PLL_is_valid(crtc,
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limit, &clock))
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continue;
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this_err = abs(clock.dot - target);
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if (this_err < err) {
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*best_clock = clock;
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err = this_err;
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}
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}
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}
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}
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return err != target;
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}
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static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target,
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int refclk,
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struct cdv_intel_clock_t *best_clock)
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{
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struct cdv_intel_clock_t clock;
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struct gma_clock_t clock;
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if (refclk == 27000) {
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if (target < 200000) {
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clock.p1 = 2;
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@ -584,7 +448,7 @@ static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct
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clock.p = clock.p1 * clock.p2;
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clock.vco = (refclk * clock.m) / clock.n;
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clock.dot = clock.vco / clock.p;
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memcpy(best_clock, &clock, sizeof(struct cdv_intel_clock_t));
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memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
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return true;
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}
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@ -1035,14 +899,14 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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int pipe = psb_intel_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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int refclk;
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struct cdv_intel_clock_t clock;
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struct gma_clock_t clock;
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u32 dpll = 0, dspcntr, pipeconf;
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bool ok;
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bool is_crt = false, is_lvds = false, is_tv = false;
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bool is_hdmi = false, is_dp = false;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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const struct cdv_intel_limit_t *limit;
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const struct gma_limit_t *limit;
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u32 ddi_select = 0;
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bool is_edp = false;
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@ -1108,12 +972,13 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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drm_mode_debug_printmodeline(adjusted_mode);
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limit = cdv_intel_limit(crtc, refclk);
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limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
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&clock);
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if (!ok) {
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dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
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DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
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adjusted_mode->clock, clock.dot);
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return 0;
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}
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@ -1612,7 +1477,7 @@ static int cdv_crtc_set_config(struct drm_mode_set *set)
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/* FIXME: why are we using this, should it be cdv_ in this tree ? */
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static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
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static void i8xx_clock(int refclk, struct gma_clock_t *clock)
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{
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clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
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clock->p = clock->p1 * clock->p2;
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@ -1630,7 +1495,7 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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u32 dpll;
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u32 fp;
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struct cdv_intel_clock_t clock;
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struct gma_clock_t clock;
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bool is_lvds;
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struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
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@ -1788,3 +1653,9 @@ const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
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.set_config = cdv_crtc_set_config,
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.destroy = cdv_intel_crtc_destroy,
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};
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const struct gma_clock_funcs cdv_clock_funcs = {
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.clock = cdv_intel_clock,
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.limit = cdv_intel_limit,
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.pll_is_valid = gma_pll_is_valid,
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};
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