ARM: tegra: clock driver development
This branch contains most fixes and enhancements to the Tegra common clock driver. The main new feature is a driver for Tegra114, which coupled with later device tree changes enables many devices on that chip, such as MMC, I2C, etc. This branch depends on a patch in: git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 Mike has stated that this branch is stable, and is aware of this dependency and merge. Mike's branch is based on v3.9-rc3, which includes a USB change which causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence, this branch pulls in v3.9-rc4 to ensure bisectability as much as possible. This branch is based on v3.9-rc4, followed by a merge of previous Tegra "soc" pull request, followed by a merge of clk-for-3.10. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRXv21AAoJEMzrak5tbycxRAsQAK0U+y5RWQJVR1wQYAuw2AhP wX/5BcpDWhH4HrFKUGp0NrVvASHv706bbvnbSsUFeKtMGqRFaiOW756B80R0mnIG xjILt64A7kXCMRJeUoXhdJtXQfzNbgGqKUsBJknVHHBw72OhYBXop5ihMWqI9Kk6 yEsr+/CB9VlV7ZbiLaAXelKuh7oSdaG8ada6qFeRCJhpVVdrFP4aGYkt0iipOBAU GBnoISkmp/ocExXlC2n5nIEE0rukJ+KyPwR1bY4+Yj2ZFXL24Nczh8cEZFrV2yz8 Sa+/6qrowGTw/wPUK+R8+vCvfzKdCYG6rrnyWwwb9UbsP6LAcYz/WB+q0puPZeuZ 2T82osvbFxjGMYWnR2Uc4CRTid1ophxGWRh810fg1UGMIK4HRMmCxrV6D5Af3FPz rXNEf3CCd4iKJQBBYXZAR1TNn5vSX/USeqXvb0810qwe2jwJsiZP5FhZH5Ogfvod W825UpmS1zmEz4MI65/CE3fxZ8SsM9Khdp4tl25YfTJ5RMjShzRdsl4BATa8nXpr nDfBb8pE2s6hyUWXbnNHw+k4jmQMreEHp+guE6LWYmqBcVlrJpq5joIHqwRl4dyD iri9unSvbOAN+fJMXti0uW8zruitfbZgfzwRwwFy1TP0DPQBWVWwN7AABFlItD6M pWI9Uf3VL5wAHZmWe6Gq =Hasc -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: clock driver development This branch contains most fixes and enhancements to the Tegra common clock driver. The main new feature is a driver for Tegra114, which coupled with later device tree changes enables many devices on that chip, such as MMC, I2C, etc. This branch depends on a patch in: git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 Mike has stated that this branch is stable, and is aware of this dependency and merge. Mike's branch is based on v3.9-rc3, which includes a USB change which causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence, this branch pulls in v3.9-rc4 to ensure bisectability as much as possible. This branch is based on v3.9-rc4, followed by a merge of previous Tegra "soc" pull request, followed by a merge of clk-for-3.10. * tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: clk: tegra: fix enum tegra114_clk to match binding clk: tegra: Remove forced clk_enable of uartd ARM: dt: Add references to tegra_car clocks clk: tegra: devicetree match for nvidia,tegra114-car clk: tegra: Implement clocks for Tegra114 ARM: tegra: Define Tegra114 CAR binding clk: tegra: Workaround for Tegra114 MSENC problem clk: tegra: Add flags to tegra_clk_periph() clk: tegra: Add new fields and PLL types for Tegra114 clk: tegra: move from a lock bit idx to a lock mask clk: tegra: Add PLL post divider table clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE clk: tegra: Add TEGRA_PLL_BYPASS flag clk: tegra: Refactor PLL programming code clk: tegra: provide dummy cpu car ops clk: tegra: defer application of init table clk: tegra: Fix cdev1 and cdev2 IDs clk: tegra: Make gr2d and gr3d clocks children of pll_c clk: tegra: Export peripheral reset functions clk: tegra: Fix periph_clk_to_bit macro Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
2b07910131
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@ -0,0 +1,303 @@
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NVIDIA Tegra114 Clock And Reset Controller
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
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for muxing and gating Tegra's clocks, and setting their rates.
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Required properties :
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- compatible : Should be "nvidia,tegra114-car"
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- reg : Should contain CAR registers location and length
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- clocks : Should contain phandle and clock specifiers for two clocks:
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the 32 KHz "32k_in", and the board-specific oscillator "osc".
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- #clock-cells : Should be 1.
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In clock consumers, this cell represents the clock ID exposed by the CAR.
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The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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registers. These IDs often match those in the CAR's RST_DEVICES registers,
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but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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this case, those clocks are assigned IDs above 160 in order to highlight
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this issue. Implementations that interpret these clock IDs as bit values
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within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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explicitly handle these special cases.
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The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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above.
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0 unassigned
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1 unassigned
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2 unassigned
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3 unassigned
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4 rtc
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5 timer
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6 uarta
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7 unassigned (register bit affects uartb and vfir)
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8 unassigned
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9 sdmmc2
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10 unassigned (register bit affects spdif_in and spdif_out)
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11 i2s1
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12 i2c1
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13 ndflash
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14 sdmmc1
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15 sdmmc4
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16 unassigned
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17 pwm
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18 i2s2
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19 epp
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20 unassigned (register bit affects vi and vi_sensor)
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21 2d
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22 usbd
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23 isp
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24 3d
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25 unassigned
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26 disp2
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27 disp1
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28 host1x
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29 vcp
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30 i2s0
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31 unassigned
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32 unassigned
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33 unassigned
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34 apbdma
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35 unassigned
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36 kbc
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37 unassigned
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38 unassigned
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39 unassigned (register bit affects fuse and fuse_burn)
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40 kfuse
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41 sbc1
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42 nor
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43 unassigned
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44 sbc2
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45 unassigned
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46 sbc3
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47 i2c5
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48 dsia
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49 unassigned
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50 mipi
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51 hdmi
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52 csi
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53 unassigned
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54 i2c2
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55 uartc
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56 mipi-cal
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57 emc
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58 usb2
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59 usb3
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60 msenc
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61 vde
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62 bsea
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63 bsev
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64 unassigned
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65 uartd
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66 unassigned
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67 i2c3
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68 sbc4
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69 sdmmc3
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70 unassigned
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71 owr
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72 afi
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73 csite
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74 unassigned
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75 unassigned
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76 la
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77 trace
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78 soc_therm
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79 dtv
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80 ndspeed
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81 i2cslow
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82 dsib
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83 tsec
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84 unassigned
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85 unassigned
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86 unassigned
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87 unassigned
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88 unassigned
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89 xusb_host
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90 unassigned
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91 msenc
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92 csus
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93 unassigned
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94 unassigned
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95 unassigned (bit affects xusb_dev and xusb_dev_src)
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96 unassigned
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97 unassigned
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98 unassigned
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99 mselect
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100 tsensor
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101 i2s3
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102 i2s4
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103 i2c4
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104 sbc5
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105 sbc6
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106 d_audio
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107 apbif
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108 dam0
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109 dam1
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110 dam2
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111 hda2codec_2x
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112 unassigned
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113 audio0_2x
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114 audio1_2x
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115 audio2_2x
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116 audio3_2x
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117 audio4_2x
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118 spdif_2x
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119 actmon
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120 extern1
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121 extern2
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122 extern3
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123 unassigned
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124 unassigned
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125 hda
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126 unassigned
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127 se
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128 hda2hdmi
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129 unassigned
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130 unassigned
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131 unassigned
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132 unassigned
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133 unassigned
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134 unassigned
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135 unassigned
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136 unassigned
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137 unassigned
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138 unassigned
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139 unassigned
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140 unassigned
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141 unassigned
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142 unassigned
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143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
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xusb_host_src and xusb_ss_src)
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144 cilab
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145 cilcd
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146 cile
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147 dsialp
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148 dsiblp
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149 unassigned
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150 dds
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151 unassigned
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152 dp2
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153 amx
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154 adx
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155 unassigned (bit affects dfll_ref and dfll_soc)
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156 xusb_ss
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192 uartb
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193 vfir
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194 spdif_in
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195 spdif_out
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196 vi
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197 vi_sensor
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198 fuse
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199 fuse_burn
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200 clk_32k
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201 clk_m
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202 clk_m_div2
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203 clk_m_div4
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204 pll_ref
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205 pll_c
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206 pll_c_out1
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207 pll_c2
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208 pll_c3
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209 pll_m
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210 pll_m_out1
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211 pll_p
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212 pll_p_out1
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213 pll_p_out2
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214 pll_p_out3
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215 pll_p_out4
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216 pll_a
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217 pll_a_out0
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218 pll_d
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219 pll_d_out0
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220 pll_d2
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221 pll_d2_out0
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222 pll_u
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223 pll_u_480M
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224 pll_u_60M
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225 pll_u_48M
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226 pll_u_12M
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227 pll_x
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228 pll_x_out0
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229 pll_re_vco
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230 pll_re_out
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231 pll_e_out0
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232 spdif_in_sync
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233 i2s0_sync
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234 i2s1_sync
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235 i2s2_sync
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236 i2s3_sync
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237 i2s4_sync
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238 vimclk_sync
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239 audio0
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240 audio1
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241 audio2
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242 audio3
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243 audio4
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244 spdif
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245 clk_out_1
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246 clk_out_2
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247 clk_out_3
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248 blink
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252 xusb_host_src
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253 xusb_falcon_src
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254 xusb_fs_src
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255 xusb_ss_src
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256 xusb_dev_src
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257 xusb_dev
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258 xusb_hs_src
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259 sclk
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260 hclk
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261 pclk
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262 cclk_g
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263 cclk_lp
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264 dfll_ref
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265 dfll_soc
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Example SoC include file:
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/ {
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tegra_car: clock {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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usb@c5004000 {
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clocks = <&tegra_car 58>; /* usb2 */
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};
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};
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Example board file:
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/ {
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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osc: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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clk_32k: clock@1 {
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compatible = "fixed-clock";
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reg = <1>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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&tegra_car {
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clocks = <&clk_32k> <&osc>;
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};
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};
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@ -120,8 +120,8 @@ Required properties :
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90 clk_d
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91 unassigned
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92 sus
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93 cdev1
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94 cdev2
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93 cdev2
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94 cdev1
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95 unassigned
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96 uart2
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@ -12,7 +12,6 @@
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serial@70006300 {
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status = "okay";
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clock-frequency = <408000000>;
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};
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pmc {
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@ -12,7 +12,6 @@
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serial@70006300 {
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status = "okay";
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clock-frequency = <408000000>;
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};
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pmc {
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@ -24,10 +24,11 @@
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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clocks = <&tegra_car 5>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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@ -66,6 +67,7 @@
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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status = "disabled";
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clocks = <&tegra_car 6>;
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};
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serial@70006040 {
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@ -74,6 +76,7 @@
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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status = "disabled";
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clocks = <&tegra_car 192>;
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};
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serial@70006200 {
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@ -82,6 +85,7 @@
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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status = "disabled";
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clocks = <&tegra_car 55>;
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};
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serial@70006300 {
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@ -90,12 +94,14 @@
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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status = "disabled";
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clocks = <&tegra_car 65>;
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};
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rtc {
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compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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clocks = <&tegra_car 4>;
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};
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pmc {
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@ -36,6 +36,7 @@
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <linux/usb/tegra_usb_phy.h>
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#include <linux/clk/tegra.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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@ -87,6 +88,8 @@ static void __init tegra_dt_init(void)
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struct soc_device *soc_dev;
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struct device *parent = NULL;
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tegra_clocks_apply_init_table();
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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goto out;
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@ -9,3 +9,4 @@ obj-y += clk-super.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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@ -41,7 +41,9 @@ static DEFINE_SPINLOCK(periph_ref_lock);
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#define write_rst_clr(val, gate) \
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writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
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#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
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#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
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#define LVL2_CLK_GATE_OVRE 0x554
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/* Peripheral gate clock ops */
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static int clk_periph_is_enabled(struct clk_hw *hw)
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@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
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}
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}
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if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
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writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
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writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
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udelay(1);
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writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
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}
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spin_unlock_irqrestore(&periph_ref_lock, flags);
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return 0;
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@ -16,6 +16,7 @@
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|||
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/export.h>
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#include <linux/slab.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
|
|
@ -128,6 +129,7 @@ void tegra_periph_reset_deassert(struct clk *c)
|
|||
|
||||
tegra_periph_reset(gate, 0);
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_periph_reset_deassert);
|
||||
|
||||
void tegra_periph_reset_assert(struct clk *c)
|
||||
{
|
||||
|
|
@ -147,6 +149,7 @@ void tegra_periph_reset_assert(struct clk *c)
|
|||
|
||||
tegra_periph_reset(gate, 1);
|
||||
}
|
||||
EXPORT_SYMBOL(tegra_periph_reset_assert);
|
||||
|
||||
const struct clk_ops tegra_clk_periph_ops = {
|
||||
.get_parent = clk_periph_get_parent,
|
||||
|
|
@ -170,14 +173,15 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
|
|||
static struct clk *_tegra_clk_register_periph(const char *name,
|
||||
const char **parent_names, int num_parents,
|
||||
struct tegra_clk_periph *periph,
|
||||
void __iomem *clk_base, u32 offset, bool div)
|
||||
void __iomem *clk_base, u32 offset, bool div,
|
||||
unsigned long flags)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
init.name = name;
|
||||
init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
|
||||
init.flags = div ? 0 : CLK_SET_RATE_PARENT;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_names;
|
||||
init.num_parents = num_parents;
|
||||
|
||||
|
|
@ -202,10 +206,10 @@ static struct clk *_tegra_clk_register_periph(const char *name,
|
|||
struct clk *tegra_clk_register_periph(const char *name,
|
||||
const char **parent_names, int num_parents,
|
||||
struct tegra_clk_periph *periph, void __iomem *clk_base,
|
||||
u32 offset)
|
||||
u32 offset, unsigned long flags)
|
||||
{
|
||||
return _tegra_clk_register_periph(name, parent_names, num_parents,
|
||||
periph, clk_base, offset, true);
|
||||
periph, clk_base, offset, true, flags);
|
||||
}
|
||||
|
||||
struct clk *tegra_clk_register_periph_nodiv(const char *name,
|
||||
|
|
@ -214,5 +218,5 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
|
|||
u32 offset)
|
||||
{
|
||||
return _tegra_clk_register_periph(name, parent_names, num_parents,
|
||||
periph, clk_base, offset, false);
|
||||
periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -86,8 +86,8 @@
|
|||
#define PLLE_BASE 0xe8
|
||||
#define PLLE_MISC 0xec
|
||||
|
||||
#define PLL_BASE_LOCK 27
|
||||
#define PLLE_MISC_LOCK 11
|
||||
#define PLL_BASE_LOCK BIT(27)
|
||||
#define PLLE_MISC_LOCK BIT(11)
|
||||
|
||||
#define PLL_MISC_LOCK_ENABLE 18
|
||||
#define PLLDU_MISC_LOCK_ENABLE 22
|
||||
|
|
@ -236,7 +236,7 @@ enum tegra20_clk {
|
|||
dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
|
||||
usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
|
||||
pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
|
||||
iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev1, cdev2,
|
||||
iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
|
||||
uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
|
||||
osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
|
||||
pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
|
||||
|
|
@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
|
|||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 600000000, 600, 12, 1, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 1, 8 },
|
||||
{ 19200000, 600000000, 500, 16, 1, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 1, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 0, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 0, 8 },
|
||||
{ 19200000, 600000000, 500, 16, 0, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{ 12000000, 666000000, 666, 12, 1, 8},
|
||||
{ 13000000, 666000000, 666, 13, 1, 8},
|
||||
{ 19200000, 666000000, 555, 16, 1, 8},
|
||||
{ 26000000, 666000000, 666, 26, 1, 8},
|
||||
{ 12000000, 600000000, 600, 12, 1, 8},
|
||||
{ 13000000, 600000000, 600, 13, 1, 8},
|
||||
{ 19200000, 600000000, 375, 12, 1, 6},
|
||||
{ 26000000, 600000000, 600, 26, 1, 8},
|
||||
{ 12000000, 666000000, 666, 12, 0, 8},
|
||||
{ 13000000, 666000000, 666, 13, 0, 8},
|
||||
{ 19200000, 666000000, 555, 16, 0, 8},
|
||||
{ 26000000, 666000000, 666, 26, 0, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{ 12000000, 216000000, 432, 12, 2, 8},
|
||||
{ 13000000, 216000000, 432, 13, 2, 8},
|
||||
{ 19200000, 216000000, 90, 4, 2, 1},
|
||||
{ 26000000, 216000000, 432, 26, 2, 8},
|
||||
{ 12000000, 432000000, 432, 12, 1, 8},
|
||||
{ 13000000, 432000000, 432, 13, 1, 8},
|
||||
{ 19200000, 432000000, 90, 4, 1, 1},
|
||||
{ 26000000, 432000000, 432, 26, 1, 8},
|
||||
{ 12000000, 216000000, 432, 12, 1, 8},
|
||||
{ 13000000, 216000000, 432, 13, 1, 8},
|
||||
{ 19200000, 216000000, 90, 4, 1, 1},
|
||||
{ 26000000, 216000000, 432, 26, 1, 8},
|
||||
{ 12000000, 432000000, 432, 12, 0, 8},
|
||||
{ 13000000, 432000000, 432, 13, 0, 8},
|
||||
{ 19200000, 432000000, 90, 4, 0, 1},
|
||||
{ 26000000, 432000000, 432, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{ 28800000, 56448000, 49, 25, 1, 1},
|
||||
{ 28800000, 73728000, 64, 25, 1, 1},
|
||||
{ 28800000, 24000000, 5, 6, 1, 1},
|
||||
{ 28800000, 56448000, 49, 25, 0, 1},
|
||||
{ 28800000, 73728000, 64, 25, 0, 1},
|
||||
{ 28800000, 24000000, 5, 6, 0, 1},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{ 12000000, 216000000, 216, 12, 1, 4},
|
||||
{ 13000000, 216000000, 216, 13, 1, 4},
|
||||
{ 19200000, 216000000, 135, 12, 1, 3},
|
||||
{ 26000000, 216000000, 216, 26, 1, 4},
|
||||
{ 12000000, 216000000, 216, 12, 0, 4},
|
||||
{ 13000000, 216000000, 216, 13, 0, 4},
|
||||
{ 19200000, 216000000, 135, 12, 0, 3},
|
||||
{ 26000000, 216000000, 216, 26, 0, 4},
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 1, 8},
|
||||
{ 13000000, 594000000, 594, 13, 1, 8},
|
||||
{ 19200000, 594000000, 495, 16, 1, 8},
|
||||
{ 26000000, 594000000, 594, 26, 1, 8},
|
||||
{ 12000000, 594000000, 594, 12, 0, 8},
|
||||
{ 13000000, 594000000, 594, 13, 0, 8},
|
||||
{ 19200000, 594000000, 495, 16, 0, 8},
|
||||
{ 26000000, 594000000, 594, 26, 0, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12},
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{ 12000000, 480000000, 960, 12, 2, 0},
|
||||
{ 13000000, 480000000, 960, 13, 2, 0},
|
||||
{ 19200000, 480000000, 200, 4, 2, 0},
|
||||
{ 26000000, 480000000, 960, 26, 2, 0},
|
||||
{ 12000000, 480000000, 960, 12, 0, 0},
|
||||
{ 13000000, 480000000, 960, 13, 0, 0},
|
||||
{ 19200000, 480000000, 200, 4, 0, 0},
|
||||
{ 26000000, 480000000, 960, 26, 0, 0},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1 GHz */
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12},
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
/* 912 MHz */
|
||||
{ 12000000, 912000000, 912, 12, 1, 12},
|
||||
{ 13000000, 912000000, 912, 13, 1, 12},
|
||||
{ 19200000, 912000000, 760, 16, 1, 8},
|
||||
{ 26000000, 912000000, 912, 26, 1, 12},
|
||||
{ 12000000, 912000000, 912, 12, 0, 12},
|
||||
{ 13000000, 912000000, 912, 13, 0, 12},
|
||||
{ 19200000, 912000000, 760, 16, 0, 8},
|
||||
{ 26000000, 912000000, 912, 26, 0, 12},
|
||||
|
||||
/* 816 MHz */
|
||||
{ 12000000, 816000000, 816, 12, 1, 12},
|
||||
{ 13000000, 816000000, 816, 13, 1, 12},
|
||||
{ 19200000, 816000000, 680, 16, 1, 8},
|
||||
{ 26000000, 816000000, 816, 26, 1, 12},
|
||||
{ 12000000, 816000000, 816, 12, 0, 12},
|
||||
{ 13000000, 816000000, 816, 13, 0, 12},
|
||||
{ 19200000, 816000000, 680, 16, 0, 8},
|
||||
{ 26000000, 816000000, 816, 26, 0, 12},
|
||||
|
||||
/* 760 MHz */
|
||||
{ 12000000, 760000000, 760, 12, 1, 12},
|
||||
{ 13000000, 760000000, 760, 13, 1, 12},
|
||||
{ 19200000, 760000000, 950, 24, 1, 8},
|
||||
{ 26000000, 760000000, 760, 26, 1, 12},
|
||||
{ 12000000, 760000000, 760, 12, 0, 12},
|
||||
{ 13000000, 760000000, 760, 13, 0, 12},
|
||||
{ 19200000, 760000000, 950, 24, 0, 8},
|
||||
{ 26000000, 760000000, 760, 26, 0, 12},
|
||||
|
||||
/* 750 MHz */
|
||||
{ 12000000, 750000000, 750, 12, 1, 12},
|
||||
{ 13000000, 750000000, 750, 13, 1, 12},
|
||||
{ 19200000, 750000000, 625, 16, 1, 8},
|
||||
{ 26000000, 750000000, 750, 26, 1, 12},
|
||||
{ 12000000, 750000000, 750, 12, 0, 12},
|
||||
{ 13000000, 750000000, 750, 13, 0, 12},
|
||||
{ 19200000, 750000000, 625, 16, 0, 8},
|
||||
{ 26000000, 750000000, 750, 26, 0, 12},
|
||||
|
||||
/* 608 MHz */
|
||||
{ 12000000, 608000000, 608, 12, 1, 12},
|
||||
{ 13000000, 608000000, 608, 13, 1, 12},
|
||||
{ 19200000, 608000000, 380, 12, 1, 8},
|
||||
{ 26000000, 608000000, 608, 26, 1, 12},
|
||||
{ 12000000, 608000000, 608, 12, 0, 12},
|
||||
{ 13000000, 608000000, 608, 13, 0, 12},
|
||||
{ 19200000, 608000000, 380, 12, 0, 8},
|
||||
{ 26000000, 608000000, 608, 26, 0, 12},
|
||||
|
||||
/* 456 MHz */
|
||||
{ 12000000, 456000000, 456, 12, 1, 12},
|
||||
{ 13000000, 456000000, 456, 13, 1, 12},
|
||||
{ 19200000, 456000000, 380, 16, 1, 8},
|
||||
{ 26000000, 456000000, 456, 26, 1, 12},
|
||||
{ 12000000, 456000000, 456, 12, 0, 12},
|
||||
{ 13000000, 456000000, 456, 13, 0, 12},
|
||||
{ 19200000, 456000000, 380, 16, 0, 8},
|
||||
{ 26000000, 456000000, 456, 26, 0, 12},
|
||||
|
||||
/* 312 MHz */
|
||||
{ 12000000, 312000000, 312, 12, 1, 12},
|
||||
{ 13000000, 312000000, 312, 13, 1, 12},
|
||||
{ 19200000, 312000000, 260, 16, 1, 8},
|
||||
{ 26000000, 312000000, 312, 26, 1, 12},
|
||||
{ 12000000, 312000000, 312, 12, 0, 12},
|
||||
{ 13000000, 312000000, 312, 13, 0, 12},
|
||||
{ 19200000, 312000000, 260, 16, 0, 8},
|
||||
{ 26000000, 312000000, 312, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
{ 12000000, 100000000, 200, 24, 1, 0 },
|
||||
{ 12000000, 100000000, 200, 24, 0, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
|
|
@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.vco_max = 1400000000,
|
||||
.base_reg = PLLC_BASE,
|
||||
.misc_reg = PLLC_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.vco_max = 1200000000,
|
||||
.base_reg = PLLM_BASE,
|
||||
.misc_reg = PLLM_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.vco_max = 1400000000,
|
||||
.base_reg = PLLP_BASE,
|
||||
.misc_reg = PLLP_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.vco_max = 1400000000,
|
||||
.base_reg = PLLA_BASE,
|
||||
.misc_reg = PLLA_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -436,11 +436,17 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.vco_max = 1000000000,
|
||||
.base_reg = PLLD_BASE,
|
||||
.misc_reg = PLLD_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 2, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_u_params = {
|
||||
.input_min = 2000000,
|
||||
.input_max = 40000000,
|
||||
|
|
@ -450,9 +456,10 @@ static struct tegra_clk_pll_params pll_u_params = {
|
|||
.vco_max = 960000000,
|
||||
.base_reg = PLLU_BASE,
|
||||
.misc_reg = PLLU_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.pdiv_tohw = pllu_p,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
|
|
@ -464,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
.vco_max = 1200000000,
|
||||
.base_reg = PLLX_BASE,
|
||||
.misc_reg = PLLX_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -478,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
.vco_max = 0,
|
||||
.base_reg = PLLE_BASE,
|
||||
.misc_reg = PLLE_MISC,
|
||||
.lock_bit_idx = PLLE_MISC_LOCK,
|
||||
.lock_mask = PLLE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 0,
|
||||
};
|
||||
|
|
@ -1012,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
|
|||
data = &tegra_periph_clk_list[i];
|
||||
clk = tegra_clk_register_periph(data->name, data->parent_names,
|
||||
data->num_parents, &data->periph,
|
||||
clk_base, data->offset);
|
||||
clk_base, data->offset, data->flags);
|
||||
clk_register_clkdev(clk, data->con_id, data->dev_id);
|
||||
clks[data->clk_id] = clk;
|
||||
}
|
||||
|
|
@ -1247,9 +1254,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
|
|||
{host1x, pll_c, 150000000, 0},
|
||||
{disp1, pll_p, 600000000, 0},
|
||||
{disp2, pll_p, 600000000, 0},
|
||||
{gr2d, pll_c, 300000000, 0},
|
||||
{gr3d, pll_c, 300000000, 0},
|
||||
{clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
|
||||
};
|
||||
|
||||
static void __init tegra20_clock_apply_init_table(void)
|
||||
{
|
||||
tegra_init_from_table(init_table, clks, clk_max);
|
||||
}
|
||||
|
||||
/*
|
||||
* Some clocks may be used by different drivers depending on the board
|
||||
* configuration. List those here to register them twice in the clock lookup
|
||||
|
|
@ -1316,7 +1330,7 @@ void __init tegra20_clock_init(struct device_node *np)
|
|||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
tegra_init_from_table(init_table, clks, clk_max);
|
||||
tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
|
||||
|
||||
tegra_cpu_car_ops = &tegra20_cpu_car_ops;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -116,8 +116,8 @@
|
|||
#define PLLDU_MISC_LOCK_ENABLE 22
|
||||
#define PLLE_MISC_LOCK_ENABLE 9
|
||||
|
||||
#define PLL_BASE_LOCK 27
|
||||
#define PLLE_MISC_LOCK 11
|
||||
#define PLL_BASE_LOCK BIT(27)
|
||||
#define PLLE_MISC_LOCK BIT(11)
|
||||
|
||||
#define PLLE_AUX 0x48c
|
||||
#define PLLC_OUT 0x84
|
||||
|
|
@ -330,7 +330,7 @@ enum tegra30_clk {
|
|||
usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
|
||||
pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
|
||||
dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
|
||||
cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
|
||||
cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
|
||||
i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
|
||||
atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
|
||||
spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
|
||||
|
|
@ -374,164 +374,170 @@ static const struct utmi_clk_param utmi_parameters[] = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 1040000000, 520, 6, 1, 8},
|
||||
{ 13000000, 1040000000, 480, 6, 1, 8},
|
||||
{ 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
|
||||
{ 19200000, 1040000000, 325, 6, 1, 6},
|
||||
{ 26000000, 1040000000, 520, 13, 1, 8},
|
||||
{ 12000000, 1040000000, 520, 6, 0, 8},
|
||||
{ 13000000, 1040000000, 480, 6, 0, 8},
|
||||
{ 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
|
||||
{ 19200000, 1040000000, 325, 6, 0, 6},
|
||||
{ 26000000, 1040000000, 520, 13, 0, 8},
|
||||
|
||||
{ 12000000, 832000000, 416, 6, 1, 8},
|
||||
{ 13000000, 832000000, 832, 13, 1, 8},
|
||||
{ 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
|
||||
{ 19200000, 832000000, 260, 6, 1, 8},
|
||||
{ 26000000, 832000000, 416, 13, 1, 8},
|
||||
{ 12000000, 832000000, 416, 6, 0, 8},
|
||||
{ 13000000, 832000000, 832, 13, 0, 8},
|
||||
{ 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
|
||||
{ 19200000, 832000000, 260, 6, 0, 8},
|
||||
{ 26000000, 832000000, 416, 13, 0, 8},
|
||||
|
||||
{ 12000000, 624000000, 624, 12, 1, 8},
|
||||
{ 13000000, 624000000, 624, 13, 1, 8},
|
||||
{ 16800000, 600000000, 520, 14, 1, 8},
|
||||
{ 19200000, 624000000, 520, 16, 1, 8},
|
||||
{ 26000000, 624000000, 624, 26, 1, 8},
|
||||
{ 12000000, 624000000, 624, 12, 0, 8},
|
||||
{ 13000000, 624000000, 624, 13, 0, 8},
|
||||
{ 16800000, 600000000, 520, 14, 0, 8},
|
||||
{ 19200000, 624000000, 520, 16, 0, 8},
|
||||
{ 26000000, 624000000, 624, 26, 0, 8},
|
||||
|
||||
{ 12000000, 600000000, 600, 12, 1, 8},
|
||||
{ 13000000, 600000000, 600, 13, 1, 8},
|
||||
{ 16800000, 600000000, 500, 14, 1, 8},
|
||||
{ 19200000, 600000000, 375, 12, 1, 6},
|
||||
{ 26000000, 600000000, 600, 26, 1, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 16800000, 600000000, 500, 14, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
|
||||
{ 12000000, 520000000, 520, 12, 1, 8},
|
||||
{ 13000000, 520000000, 520, 13, 1, 8},
|
||||
{ 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
|
||||
{ 19200000, 520000000, 325, 12, 1, 6},
|
||||
{ 26000000, 520000000, 520, 26, 1, 8},
|
||||
{ 12000000, 520000000, 520, 12, 0, 8},
|
||||
{ 13000000, 520000000, 520, 13, 0, 8},
|
||||
{ 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
|
||||
{ 19200000, 520000000, 325, 12, 0, 6},
|
||||
{ 26000000, 520000000, 520, 26, 0, 8},
|
||||
|
||||
{ 12000000, 416000000, 416, 12, 1, 8},
|
||||
{ 13000000, 416000000, 416, 13, 1, 8},
|
||||
{ 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
|
||||
{ 19200000, 416000000, 260, 12, 1, 6},
|
||||
{ 26000000, 416000000, 416, 26, 1, 8},
|
||||
{ 12000000, 416000000, 416, 12, 0, 8},
|
||||
{ 13000000, 416000000, 416, 13, 0, 8},
|
||||
{ 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
|
||||
{ 19200000, 416000000, 260, 12, 0, 6},
|
||||
{ 26000000, 416000000, 416, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{ 12000000, 666000000, 666, 12, 1, 8},
|
||||
{ 13000000, 666000000, 666, 13, 1, 8},
|
||||
{ 16800000, 666000000, 555, 14, 1, 8},
|
||||
{ 19200000, 666000000, 555, 16, 1, 8},
|
||||
{ 26000000, 666000000, 666, 26, 1, 8},
|
||||
{ 12000000, 600000000, 600, 12, 1, 8},
|
||||
{ 13000000, 600000000, 600, 13, 1, 8},
|
||||
{ 16800000, 600000000, 500, 14, 1, 8},
|
||||
{ 19200000, 600000000, 375, 12, 1, 6},
|
||||
{ 26000000, 600000000, 600, 26, 1, 8},
|
||||
{ 12000000, 666000000, 666, 12, 0, 8},
|
||||
{ 13000000, 666000000, 666, 13, 0, 8},
|
||||
{ 16800000, 666000000, 555, 14, 0, 8},
|
||||
{ 19200000, 666000000, 555, 16, 0, 8},
|
||||
{ 26000000, 666000000, 666, 26, 0, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 16800000, 600000000, 500, 14, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{ 12000000, 216000000, 432, 12, 2, 8},
|
||||
{ 13000000, 216000000, 432, 13, 2, 8},
|
||||
{ 16800000, 216000000, 360, 14, 2, 8},
|
||||
{ 19200000, 216000000, 360, 16, 2, 8},
|
||||
{ 26000000, 216000000, 432, 26, 2, 8},
|
||||
{ 12000000, 216000000, 432, 12, 1, 8},
|
||||
{ 13000000, 216000000, 432, 13, 1, 8},
|
||||
{ 16800000, 216000000, 360, 14, 1, 8},
|
||||
{ 19200000, 216000000, 360, 16, 1, 8},
|
||||
{ 26000000, 216000000, 432, 26, 1, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{ 9600000, 564480000, 294, 5, 1, 4},
|
||||
{ 9600000, 552960000, 288, 5, 1, 4},
|
||||
{ 9600000, 24000000, 5, 2, 1, 1},
|
||||
{ 9600000, 564480000, 294, 5, 0, 4},
|
||||
{ 9600000, 552960000, 288, 5, 0, 4},
|
||||
{ 9600000, 24000000, 5, 2, 0, 1},
|
||||
|
||||
{ 28800000, 56448000, 49, 25, 1, 1},
|
||||
{ 28800000, 73728000, 64, 25, 1, 1},
|
||||
{ 28800000, 24000000, 5, 6, 1, 1},
|
||||
{ 28800000, 56448000, 49, 25, 0, 1},
|
||||
{ 28800000, 73728000, 64, 25, 0, 1},
|
||||
{ 28800000, 24000000, 5, 6, 0, 1},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{ 12000000, 216000000, 216, 12, 1, 4},
|
||||
{ 13000000, 216000000, 216, 13, 1, 4},
|
||||
{ 16800000, 216000000, 180, 14, 1, 4},
|
||||
{ 19200000, 216000000, 180, 16, 1, 4},
|
||||
{ 26000000, 216000000, 216, 26, 1, 4},
|
||||
{ 12000000, 216000000, 216, 12, 0, 4},
|
||||
{ 13000000, 216000000, 216, 13, 0, 4},
|
||||
{ 16800000, 216000000, 180, 14, 0, 4},
|
||||
{ 19200000, 216000000, 180, 16, 0, 4},
|
||||
{ 26000000, 216000000, 216, 26, 0, 4},
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 1, 8},
|
||||
{ 13000000, 594000000, 594, 13, 1, 8},
|
||||
{ 16800000, 594000000, 495, 14, 1, 8},
|
||||
{ 19200000, 594000000, 495, 16, 1, 8},
|
||||
{ 26000000, 594000000, 594, 26, 1, 8},
|
||||
{ 12000000, 594000000, 594, 12, 0, 8},
|
||||
{ 13000000, 594000000, 594, 13, 0, 8},
|
||||
{ 16800000, 594000000, 495, 14, 0, 8},
|
||||
{ 19200000, 594000000, 495, 16, 0, 8},
|
||||
{ 26000000, 594000000, 594, 26, 0, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12},
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 1 },
|
||||
{ .pdiv = 2, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{ 12000000, 480000000, 960, 12, 2, 12},
|
||||
{ 13000000, 480000000, 960, 13, 2, 12},
|
||||
{ 16800000, 480000000, 400, 7, 2, 5},
|
||||
{ 19200000, 480000000, 200, 4, 2, 3},
|
||||
{ 26000000, 480000000, 960, 26, 2, 12},
|
||||
{ 12000000, 480000000, 960, 12, 0, 12},
|
||||
{ 13000000, 480000000, 960, 13, 0, 12},
|
||||
{ 16800000, 480000000, 400, 7, 0, 5},
|
||||
{ 19200000, 480000000, 200, 4, 0, 3},
|
||||
{ 26000000, 480000000, 960, 26, 0, 12},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1.7 GHz */
|
||||
{ 12000000, 1700000000, 850, 6, 1, 8},
|
||||
{ 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
|
||||
{ 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
|
||||
{ 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
|
||||
{ 26000000, 1700000000, 850, 13, 1, 8},
|
||||
{ 12000000, 1700000000, 850, 6, 0, 8},
|
||||
{ 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 26000000, 1700000000, 850, 13, 0, 8},
|
||||
|
||||
/* 1.6 GHz */
|
||||
{ 12000000, 1600000000, 800, 6, 1, 8},
|
||||
{ 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
|
||||
{ 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
|
||||
{ 19200000, 1600000000, 500, 6, 1, 8},
|
||||
{ 26000000, 1600000000, 800, 13, 1, 8},
|
||||
{ 12000000, 1600000000, 800, 6, 0, 8},
|
||||
{ 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
|
||||
{ 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
|
||||
{ 19200000, 1600000000, 500, 6, 0, 8},
|
||||
{ 26000000, 1600000000, 800, 13, 0, 8},
|
||||
|
||||
/* 1.5 GHz */
|
||||
{ 12000000, 1500000000, 750, 6, 1, 8},
|
||||
{ 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
|
||||
{ 16800000, 1500000000, 625, 7, 1, 8},
|
||||
{ 19200000, 1500000000, 625, 8, 1, 8},
|
||||
{ 26000000, 1500000000, 750, 13, 1, 8},
|
||||
{ 12000000, 1500000000, 750, 6, 0, 8},
|
||||
{ 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
|
||||
{ 16800000, 1500000000, 625, 7, 0, 8},
|
||||
{ 19200000, 1500000000, 625, 8, 0, 8},
|
||||
{ 26000000, 1500000000, 750, 13, 0, 8},
|
||||
|
||||
/* 1.4 GHz */
|
||||
{ 12000000, 1400000000, 700, 6, 1, 8},
|
||||
{ 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
|
||||
{ 16800000, 1400000000, 1000, 12, 1, 8},
|
||||
{ 19200000, 1400000000, 875, 12, 1, 8},
|
||||
{ 26000000, 1400000000, 700, 13, 1, 8},
|
||||
{ 12000000, 1400000000, 700, 6, 0, 8},
|
||||
{ 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
|
||||
{ 16800000, 1400000000, 1000, 12, 0, 8},
|
||||
{ 19200000, 1400000000, 875, 12, 0, 8},
|
||||
{ 26000000, 1400000000, 700, 13, 0, 8},
|
||||
|
||||
/* 1.3 GHz */
|
||||
{ 12000000, 1300000000, 975, 9, 1, 8},
|
||||
{ 13000000, 1300000000, 1000, 10, 1, 8},
|
||||
{ 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
|
||||
{ 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
|
||||
{ 26000000, 1300000000, 650, 13, 1, 8},
|
||||
{ 12000000, 1300000000, 975, 9, 0, 8},
|
||||
{ 13000000, 1300000000, 1000, 10, 0, 8},
|
||||
{ 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
|
||||
{ 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
|
||||
{ 26000000, 1300000000, 650, 13, 0, 8},
|
||||
|
||||
/* 1.2 GHz */
|
||||
{ 12000000, 1200000000, 1000, 10, 1, 8},
|
||||
{ 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
|
||||
{ 16800000, 1200000000, 1000, 14, 1, 8},
|
||||
{ 19200000, 1200000000, 1000, 16, 1, 8},
|
||||
{ 26000000, 1200000000, 600, 13, 1, 8},
|
||||
{ 12000000, 1200000000, 1000, 10, 0, 8},
|
||||
{ 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
|
||||
{ 16800000, 1200000000, 1000, 14, 0, 8},
|
||||
{ 19200000, 1200000000, 1000, 16, 0, 8},
|
||||
{ 26000000, 1200000000, 600, 13, 0, 8},
|
||||
|
||||
/* 1.1 GHz */
|
||||
{ 12000000, 1100000000, 825, 9, 1, 8},
|
||||
{ 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
|
||||
{ 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
|
||||
{ 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
|
||||
{ 26000000, 1100000000, 550, 13, 1, 8},
|
||||
{ 12000000, 1100000000, 825, 9, 0, 8},
|
||||
{ 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
|
||||
{ 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
|
||||
{ 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
|
||||
{ 26000000, 1100000000, 550, 13, 0, 8},
|
||||
|
||||
/* 1 GHz */
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 8},
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 8},
|
||||
{ 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
|
||||
{ 19200000, 1000000000, 625, 12, 1, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 8},
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 8},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 8},
|
||||
{ 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 8},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
|
@ -553,7 +559,7 @@ static struct tegra_clk_pll_params pll_c_params = {
|
|||
.vco_max = 1400000000,
|
||||
.base_reg = PLLC_BASE,
|
||||
.misc_reg = PLLC_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -567,7 +573,7 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
.vco_max = 1200000000,
|
||||
.base_reg = PLLM_BASE,
|
||||
.misc_reg = PLLM_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -581,7 +587,7 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
.vco_max = 1400000000,
|
||||
.base_reg = PLLP_BASE,
|
||||
.misc_reg = PLLP_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -595,7 +601,7 @@ static struct tegra_clk_pll_params pll_a_params = {
|
|||
.vco_max = 1400000000,
|
||||
.base_reg = PLLA_BASE,
|
||||
.misc_reg = PLLA_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -609,7 +615,7 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
.vco_max = 1000000000,
|
||||
.base_reg = PLLD_BASE,
|
||||
.misc_reg = PLLD_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
};
|
||||
|
|
@ -623,7 +629,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
|
|||
.vco_max = 1000000000,
|
||||
.base_reg = PLLD2_BASE,
|
||||
.misc_reg = PLLD2_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
};
|
||||
|
|
@ -637,9 +643,10 @@ static struct tegra_clk_pll_params pll_u_params = {
|
|||
.vco_max = 960000000,
|
||||
.base_reg = PLLU_BASE,
|
||||
.misc_reg = PLLU_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 1000,
|
||||
.pdiv_tohw = pllu_p,
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
|
|
@ -651,7 +658,7 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
.vco_max = 1700000000,
|
||||
.base_reg = PLLX_BASE,
|
||||
.misc_reg = PLLX_MISC,
|
||||
.lock_bit_idx = PLL_BASE_LOCK,
|
||||
.lock_mask = PLL_BASE_LOCK,
|
||||
.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -665,7 +672,7 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
.vco_max = 2400000000U,
|
||||
.base_reg = PLLE_BASE,
|
||||
.misc_reg = PLLE_MISC,
|
||||
.lock_bit_idx = PLLE_MISC_LOCK,
|
||||
.lock_mask = PLLE_MISC_LOCK,
|
||||
.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
|
||||
.lock_delay = 300,
|
||||
};
|
||||
|
|
@ -1661,7 +1668,7 @@ static void __init tegra30_periph_clk_init(void)
|
|||
data = &tegra_periph_clk_list[i];
|
||||
clk = tegra_clk_register_periph(data->name, data->parent_names,
|
||||
data->num_parents, &data->periph,
|
||||
clk_base, data->offset);
|
||||
clk_base, data->offset, data->flags);
|
||||
clk_register_clkdev(clk, data->con_id, data->dev_id);
|
||||
clks[data->clk_id] = clk;
|
||||
}
|
||||
|
|
@ -1911,9 +1918,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
|
|||
{disp1, pll_p, 600000000, 0},
|
||||
{disp2, pll_p, 600000000, 0},
|
||||
{twd, clk_max, 0, 1},
|
||||
{gr2d, pll_c, 300000000, 0},
|
||||
{gr3d, pll_c, 300000000, 0},
|
||||
{clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
|
||||
};
|
||||
|
||||
static void __init tegra30_clock_apply_init_table(void)
|
||||
{
|
||||
tegra_init_from_table(init_table, clks, clk_max);
|
||||
}
|
||||
|
||||
/*
|
||||
* Some clocks may be used by different drivers depending on the board
|
||||
* configuration. List those here to register them twice in the clock lookup
|
||||
|
|
@ -1987,7 +2001,7 @@ void __init tegra30_clock_init(struct device_node *np)
|
|||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
tegra_init_from_table(init_table, clks, clk_max);
|
||||
tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
|
||||
|
||||
tegra_cpu_car_ops = &tegra30_cpu_car_ops;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,8 @@
|
|||
#include "clk.h"
|
||||
|
||||
/* Global data of Tegra CPU CAR ops */
|
||||
struct tegra_cpu_car_ops *tegra_cpu_car_ops;
|
||||
static struct tegra_cpu_car_ops dummy_car_ops;
|
||||
struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
|
||||
|
||||
void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
|
||||
struct clk *clks[], int clk_max)
|
||||
|
|
@ -76,6 +77,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
|
|||
static const struct of_device_id tegra_dt_clk_match[] = {
|
||||
{ .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
|
||||
{ .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
|
||||
{ .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -83,3 +85,13 @@ void __init tegra_clocks_init(void)
|
|||
{
|
||||
of_clk_init(tegra_dt_clk_match);
|
||||
}
|
||||
|
||||
tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
|
||||
|
||||
void __init tegra_clocks_apply_init_table(void)
|
||||
{
|
||||
if (!tegra_clk_apply_init_table)
|
||||
return;
|
||||
|
||||
tegra_clk_apply_init_table();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
|
|
@ -116,6 +116,17 @@ struct tegra_clk_pll_freq_table {
|
|||
u8 cpcon;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pdiv_map - map post divider to hw value
|
||||
*
|
||||
* @pdiv: post divider
|
||||
* @hw_val: value to be written to the PLL hw
|
||||
*/
|
||||
struct pdiv_map {
|
||||
u8 pdiv;
|
||||
u8 hw_val;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_pll_params - PLL parameters
|
||||
*
|
||||
|
|
@ -143,9 +154,18 @@ struct tegra_clk_pll_params {
|
|||
u32 base_reg;
|
||||
u32 misc_reg;
|
||||
u32 lock_reg;
|
||||
u32 lock_bit_idx;
|
||||
u32 lock_mask;
|
||||
u32 lock_enable_bit_idx;
|
||||
u32 iddq_reg;
|
||||
u32 iddq_bit_idx;
|
||||
u32 aux_reg;
|
||||
u32 dyn_ramp_reg;
|
||||
u32 ext_misc_reg[3];
|
||||
int stepa_shift;
|
||||
int stepb_shift;
|
||||
int lock_delay;
|
||||
int max_p;
|
||||
struct pdiv_map *pdiv_tohw;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -182,12 +202,16 @@ struct tegra_clk_pll_params {
|
|||
* TEGRA_PLL_FIXED - We are not supposed to change output frequency
|
||||
* of some plls.
|
||||
* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
|
||||
* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
|
||||
* base register.
|
||||
* TEGRA_PLL_BYPASS - PLL has bypass bit
|
||||
* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
|
||||
*/
|
||||
struct tegra_clk_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *clk_base;
|
||||
void __iomem *pmc;
|
||||
u8 flags;
|
||||
u32 flags;
|
||||
unsigned long fixed_rate;
|
||||
spinlock_t *lock;
|
||||
u8 divn_shift;
|
||||
|
|
@ -210,20 +234,64 @@ struct tegra_clk_pll {
|
|||
#define TEGRA_PLLM BIT(5)
|
||||
#define TEGRA_PLL_FIXED BIT(6)
|
||||
#define TEGRA_PLLE_CONFIGURE BIT(7)
|
||||
#define TEGRA_PLL_LOCK_MISC BIT(8)
|
||||
#define TEGRA_PLL_BYPASS BIT(9)
|
||||
#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
|
||||
|
||||
extern const struct clk_ops tegra_clk_pll_ops;
|
||||
extern const struct clk_ops tegra_clk_plle_ops;
|
||||
struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
|
||||
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params, u8 pll_flags,
|
||||
struct tegra_clk_pll_params *pll_params, u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
|
||||
void __iomem *clk_base, void __iomem *pmc,
|
||||
unsigned long flags, unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
u32 pll_flags,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock, unsigned long parent_rate);
|
||||
|
||||
struct clk *tegra_clk_register_plle_tegra114(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *clk_base, unsigned long flags,
|
||||
unsigned long fixed_rate,
|
||||
struct tegra_clk_pll_params *pll_params,
|
||||
struct tegra_clk_pll_freq_table *freq_table,
|
||||
spinlock_t *lock);
|
||||
|
||||
/**
|
||||
* struct tegra_clk_pll_out - PLL divider down clock
|
||||
*
|
||||
|
|
@ -290,6 +358,7 @@ struct tegra_clk_periph_regs {
|
|||
* TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
|
||||
* bus to flush the write operation in apb bus. This flag indicates
|
||||
* that this peripheral is in apb bus.
|
||||
* TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
|
||||
*/
|
||||
struct tegra_clk_periph_gate {
|
||||
u32 magic;
|
||||
|
|
@ -309,6 +378,7 @@ struct tegra_clk_periph_gate {
|
|||
#define TEGRA_PERIPH_NO_RESET BIT(0)
|
||||
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
|
||||
#define TEGRA_PERIPH_ON_APB BIT(2)
|
||||
#define TEGRA_PERIPH_WAR_1005168 BIT(3)
|
||||
|
||||
void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
|
||||
extern const struct clk_ops tegra_clk_periph_gate_ops;
|
||||
|
|
@ -349,7 +419,7 @@ extern const struct clk_ops tegra_clk_periph_ops;
|
|||
struct clk *tegra_clk_register_periph(const char *name,
|
||||
const char **parent_names, int num_parents,
|
||||
struct tegra_clk_periph *periph, void __iomem *clk_base,
|
||||
u32 offset);
|
||||
u32 offset, unsigned long flags);
|
||||
struct clk *tegra_clk_register_periph_nodiv(const char *name,
|
||||
const char **parent_names, int num_parents,
|
||||
struct tegra_clk_periph *periph, void __iomem *clk_base,
|
||||
|
|
@ -392,12 +462,14 @@ struct tegra_periph_init_data {
|
|||
u32 offset;
|
||||
const char *con_id;
|
||||
const char *dev_id;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
|
||||
_mux_shift, _mux_mask, _mux_flags, _div_shift, \
|
||||
_div_width, _div_frac_width, _div_flags, _regs, \
|
||||
_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
|
||||
_clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\
|
||||
_flags) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.clk_id = _clk_id, \
|
||||
|
|
@ -412,6 +484,7 @@ struct tegra_periph_init_data {
|
|||
.offset = _offset, \
|
||||
.con_id = _con_id, \
|
||||
.dev_id = _dev_id, \
|
||||
.flags = _flags \
|
||||
}
|
||||
|
||||
#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
|
||||
|
|
@ -422,7 +495,7 @@ struct tegra_periph_init_data {
|
|||
_mux_shift, BIT(_mux_width) - 1, _mux_flags, \
|
||||
_div_shift, _div_width, _div_frac_width, _div_flags, \
|
||||
_regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
|
||||
NULL)
|
||||
NULL, 0)
|
||||
|
||||
/**
|
||||
* struct clk_super_mux - super clock
|
||||
|
|
@ -510,4 +583,13 @@ void tegra30_clock_init(struct device_node *np);
|
|||
static inline void tegra30_clock_init(struct device_node *np) {}
|
||||
#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_114_SOC
|
||||
void tegra114_clock_init(struct device_node *np);
|
||||
#else
|
||||
static inline void tegra114_clock_init(struct device_node *np) {}
|
||||
#endif /* CONFIG_ARCH_TEGRA114_SOC */
|
||||
|
||||
typedef void (*tegra_clk_apply_init_table_func)(void);
|
||||
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
|
||||
|
||||
#endif /* TEGRA_CLK_H */
|
||||
|
|
|
|||
|
|
@ -123,5 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
|
|||
void tegra_periph_reset_deassert(struct clk *c);
|
||||
void tegra_periph_reset_assert(struct clk *c);
|
||||
void tegra_clocks_init(void);
|
||||
void tegra_clocks_apply_init_table(void);
|
||||
|
||||
#endif /* __LINUX_CLK_TEGRA_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue