ASoC: fsl-ssi: Remove fsl_ssi_setup
fsl_ssi_set_dai_fmt() manages most of the register setup routines now. fsl_ssi_setup() makes the same as fsl_ssi_set_dai_fmt() but it relies on DT properties. In most cases the settings of fsl_ssi_setup() are already overwritten by fsl_ssi_set_dai_fmt() when it is called by the soc-core when a sound card is added. As these settings depend on the combination of codec and cpu DAI, this should really be done by sound cards. This patch removes fsl_ssi_setup() and adds the missing register setups to fsl_ssi_set_dai_fmt(). It also removes all calls to fsl_ssi_setup(). Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org>hifive-unleashed-5.1
Markus Pargmann
Mark Brown
parent
c9eaa447e7
commit
2b0db996ba
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@ -642,96 +642,6 @@ static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
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write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
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}
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static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
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{
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struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
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u8 wm;
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int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
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fsl_ssi_setup_reg_vals(ssi_private);
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if (ssi_private->imx_ac97)
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ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
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else
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ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
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/*
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* Section 16.5 of the MPC8610 reference manual says that the SSI needs
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* to be disabled before updating the registers we set here.
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*/
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write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
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/*
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* Program the SSI into I2S Slave Non-Network Synchronous mode. Also
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* enable the transmit and receive FIFO.
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*
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* FIXME: Little-endian samples require a different shift dir
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*/
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write_ssi_mask(&ssi->scr,
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CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
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CCSR_SSI_SCR_TFR_CLK_DIS |
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ssi_private->i2s_mode |
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(synchronous ? CCSR_SSI_SCR_SYN : 0));
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write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
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CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
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write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
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CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
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/*
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* The DC and PM bits are only used if the SSI is the clock master.
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*/
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/*
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* Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
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* use FIFO 1. We program the transmit water to signal a DMA transfer
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* if there are only two (or fewer) elements left in the FIFO. Two
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* elements equals one frame (left channel, right channel). This value,
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* however, depends on the depth of the transmit buffer.
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*
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* We set the watermark on the same level as the DMA burstsize. For
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* fiq it is probably better to use the biggest possible watermark
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* size.
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*/
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if (ssi_private->use_dma)
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wm = ssi_private->fifo_depth - 2;
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else
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wm = ssi_private->fifo_depth;
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write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
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CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
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&ssi->sfcsr);
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/*
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* For ac97 interrupts are enabled with the startup of the substream
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* because it is also running without an active substream. Normally SSI
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* is only enabled when there is a substream.
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*/
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if (ssi_private->imx_ac97)
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fsl_ssi_setup_ac97(ssi_private);
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/*
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* Set a default slot number so that there is no need for those common
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* cases like I2S mode to call the extra set_tdm_slot() any more.
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*/
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if (!ssi_private->imx_ac97) {
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write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
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CCSR_SSI_SxCCR_DC(2));
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write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
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CCSR_SSI_SxCCR_DC(2));
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}
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if (ssi_private->use_dual_fifo) {
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write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
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write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
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write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
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}
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return 0;
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}
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/**
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* fsl_ssi_startup: create a new substream
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*
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@ -748,12 +658,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
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snd_soc_dai_get_drvdata(rtd->cpu_dai);
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unsigned long flags;
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/* First, we only do fsl_ssi_setup() when SSI is going to be active.
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* Second, fsl_ssi_setup was already called by ac97_init earlier if
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* the driver is in ac97 mode.
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*/
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if (!dai->active && !ssi_private->imx_ac97) {
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fsl_ssi_setup(ssi_private);
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spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
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ssi_private->baudclk_locked = false;
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spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
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@ -835,6 +740,9 @@ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
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struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
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u32 strcr = 0, stcr, srcr, scr, mask;
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u8 wm;
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fsl_ssi_setup_reg_vals(ssi_private);
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scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
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scr |= CCSR_SSI_SCR_NET;
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@ -857,7 +765,6 @@ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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default:
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return -EINVAL;
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}
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scr |= ssi_private->i2s_mode;
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/* Data on rising edge of bclk, frame low, 1clk before data */
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strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
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@ -877,9 +784,13 @@ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
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CCSR_SSI_STCR_TXBIT0;
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break;
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case SND_SOC_DAIFMT_AC97:
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ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL;
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break;
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default:
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return -EINVAL;
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}
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scr |= ssi_private->i2s_mode;
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/* DAI clock inversion */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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@ -929,6 +840,38 @@ static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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write_ssi(srcr, &ssi->srcr);
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write_ssi(scr, &ssi->scr);
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/*
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* Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
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* use FIFO 1. We program the transmit water to signal a DMA transfer
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* if there are only two (or fewer) elements left in the FIFO. Two
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* elements equals one frame (left channel, right channel). This value,
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* however, depends on the depth of the transmit buffer.
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*
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* We set the watermark on the same level as the DMA burstsize. For
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* fiq it is probably better to use the biggest possible watermark
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* size.
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*/
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if (ssi_private->use_dma)
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wm = ssi_private->fifo_depth - 2;
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else
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wm = ssi_private->fifo_depth;
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write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
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CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
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&ssi->sfcsr);
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if (ssi_private->use_dual_fifo) {
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write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1,
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CCSR_SSI_SRCR_RFEN1);
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write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1,
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CCSR_SSI_STCR_TFEN1);
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write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN,
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CCSR_SSI_SCR_TCH_EN);
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}
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if (fmt & SND_SOC_DAIFMT_AC97)
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fsl_ssi_setup_ac97(ssi_private);
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return 0;
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}
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@ -1184,11 +1127,6 @@ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
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static struct fsl_ssi_private *fsl_ac97_data;
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static void fsl_ssi_ac97_init(void)
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{
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fsl_ssi_setup(fsl_ac97_data);
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}
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static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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@ -1547,9 +1485,6 @@ static int fsl_ssi_probe(struct platform_device *pdev)
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}
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done:
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if (ssi_private->imx_ac97)
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fsl_ssi_ac97_init();
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return 0;
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error_dai:
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