sh: Preliminary support for the SH-X3 CPU.
This adds basic support for UP SH-X3. Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
Paul Mundt
parent
027e56e685
commit
2b1bd1ac5d
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@ -598,6 +598,7 @@ config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP
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default "4" if CPU_SHX3
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default "2"
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help
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This allows you to specify the maximum number of CPUs which this
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@ -0,0 +1,756 @@
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#
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# Automatically generated make config: don't edit
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# Linux kernel version: 2.6.22-rc4
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# Wed Jun 20 14:09:27 2007
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#
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CONFIG_SUPERH=y
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CONFIG_RWSEM_GENERIC_SPINLOCK=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_HWEIGHT=y
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CONFIG_GENERIC_HARDIRQS=y
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CONFIG_GENERIC_IRQ_PROBE=y
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CONFIG_GENERIC_CALIBRATE_DELAY=y
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CONFIG_GENERIC_TIME=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_STACKTRACE_SUPPORT=y
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CONFIG_LOCKDEP_SUPPORT=y
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
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#
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# Code maturity level options
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#
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CONFIG_EXPERIMENTAL=y
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CONFIG_BROKEN_ON_SMP=y
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CONFIG_LOCK_KERNEL=y
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CONFIG_INIT_ENV_ARG_LIMIT=32
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#
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# General setup
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#
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CONFIG_LOCALVERSION=""
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CONFIG_LOCALVERSION_AUTO=y
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CONFIG_SWAP=y
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CONFIG_SYSVIPC=y
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# CONFIG_IPC_NS is not set
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CONFIG_SYSVIPC_SYSCTL=y
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CONFIG_BSD_PROCESS_ACCT=y
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# CONFIG_BSD_PROCESS_ACCT_V3 is not set
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# CONFIG_UTS_NS is not set
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=14
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# CONFIG_SYSFS_DEPRECATED is not set
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# CONFIG_RELAY is not set
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_SYSCTL=y
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CONFIG_EMBEDDED=y
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CONFIG_UID16=y
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CONFIG_SYSCTL_SYSCALL=y
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CONFIG_KALLSYMS=y
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CONFIG_KALLSYMS_ALL=y
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# CONFIG_KALLSYMS_EXTRA_PASS is not set
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CONFIG_HOTPLUG=y
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CONFIG_PRINTK=y
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CONFIG_BUG=y
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CONFIG_ELF_CORE=y
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CONFIG_BASE_FULL=y
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CONFIG_FUTEX=y
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CONFIG_ANON_INODES=y
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CONFIG_EPOLL=y
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CONFIG_SIGNALFD=y
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CONFIG_TIMERFD=y
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CONFIG_EVENTFD=y
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CONFIG_SHMEM=y
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CONFIG_VM_EVENT_COUNTERS=y
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CONFIG_SLAB=y
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# CONFIG_SLUB is not set
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# CONFIG_SLOB is not set
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CONFIG_RT_MUTEXES=y
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# CONFIG_TINY_SHMEM is not set
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CONFIG_BASE_SMALL=0
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#
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# Loadable module support
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#
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_MODULE_FORCE_UNLOAD is not set
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# CONFIG_MODVERSIONS is not set
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# CONFIG_MODULE_SRCVERSION_ALL is not set
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CONFIG_KMOD=y
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#
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# Block layer
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#
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CONFIG_BLOCK=y
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# CONFIG_LBD is not set
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# CONFIG_BLK_DEV_IO_TRACE is not set
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# CONFIG_LSF is not set
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#
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# IO Schedulers
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#
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CONFIG_IOSCHED_NOOP=y
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# CONFIG_IOSCHED_AS is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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# CONFIG_DEFAULT_AS is not set
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# CONFIG_DEFAULT_DEADLINE is not set
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# CONFIG_DEFAULT_CFQ is not set
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CONFIG_DEFAULT_NOOP=y
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CONFIG_DEFAULT_IOSCHED="noop"
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#
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# System type
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#
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CONFIG_CPU_SH4=y
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CONFIG_CPU_SH4A=y
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CONFIG_CPU_SHX3=y
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# CONFIG_CPU_SUBTYPE_SH7619 is not set
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# CONFIG_CPU_SUBTYPE_SH7206 is not set
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# CONFIG_CPU_SUBTYPE_SH7300 is not set
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# CONFIG_CPU_SUBTYPE_SH7705 is not set
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# CONFIG_CPU_SUBTYPE_SH7706 is not set
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# CONFIG_CPU_SUBTYPE_SH7707 is not set
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# CONFIG_CPU_SUBTYPE_SH7708 is not set
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# CONFIG_CPU_SUBTYPE_SH7709 is not set
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# CONFIG_CPU_SUBTYPE_SH7710 is not set
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# CONFIG_CPU_SUBTYPE_SH7712 is not set
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# CONFIG_CPU_SUBTYPE_SH7750 is not set
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# CONFIG_CPU_SUBTYPE_SH7091 is not set
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# CONFIG_CPU_SUBTYPE_SH7750R is not set
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# CONFIG_CPU_SUBTYPE_SH7750S is not set
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# CONFIG_CPU_SUBTYPE_SH7751 is not set
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# CONFIG_CPU_SUBTYPE_SH7751R is not set
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# CONFIG_CPU_SUBTYPE_SH7760 is not set
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# CONFIG_CPU_SUBTYPE_SH4_202 is not set
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# CONFIG_CPU_SUBTYPE_ST40STB1 is not set
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# CONFIG_CPU_SUBTYPE_ST40GX1 is not set
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# CONFIG_CPU_SUBTYPE_SH7770 is not set
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# CONFIG_CPU_SUBTYPE_SH7780 is not set
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# CONFIG_CPU_SUBTYPE_SH7785 is not set
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CONFIG_CPU_SUBTYPE_SHX3=y
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# CONFIG_CPU_SUBTYPE_SH73180 is not set
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# CONFIG_CPU_SUBTYPE_SH7343 is not set
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# CONFIG_CPU_SUBTYPE_SH7722 is not set
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#
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# Memory management options
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#
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CONFIG_QUICKLIST=y
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CONFIG_MMU=y
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CONFIG_PAGE_OFFSET=0x80000000
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CONFIG_MEMORY_START=0x0c000000
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CONFIG_MEMORY_SIZE=0x04000000
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CONFIG_VSYSCALL=y
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CONFIG_ARCH_FLATMEM_ENABLE=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_SPARSEMEM_DEFAULT=y
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CONFIG_MAX_ACTIVE_REGIONS=1
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CONFIG_ARCH_POPULATES_NODE_MAP=y
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CONFIG_ARCH_SELECT_MEMORY_MODEL=y
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CONFIG_PAGE_SIZE_4KB=y
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# CONFIG_PAGE_SIZE_8KB is not set
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# CONFIG_PAGE_SIZE_64KB is not set
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CONFIG_HUGETLB_PAGE_SIZE_64K=y
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# CONFIG_HUGETLB_PAGE_SIZE_256K is not set
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# CONFIG_HUGETLB_PAGE_SIZE_1MB is not set
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# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set
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# CONFIG_HUGETLB_PAGE_SIZE_64MB is not set
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CONFIG_SELECT_MEMORY_MODEL=y
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CONFIG_FLATMEM_MANUAL=y
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# CONFIG_DISCONTIGMEM_MANUAL is not set
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# CONFIG_SPARSEMEM_MANUAL is not set
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CONFIG_FLATMEM=y
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CONFIG_FLAT_NODE_MEM_MAP=y
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CONFIG_SPARSEMEM_STATIC=y
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CONFIG_SPLIT_PTLOCK_CPUS=4
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# CONFIG_RESOURCES_64BIT is not set
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CONFIG_ZONE_DMA_FLAG=0
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CONFIG_NR_QUICK=2
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#
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# Cache configuration
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#
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# CONFIG_SH_DIRECT_MAPPED is not set
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# CONFIG_SH_WRITETHROUGH is not set
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#
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# Processor features
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#
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CONFIG_CPU_LITTLE_ENDIAN=y
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# CONFIG_CPU_BIG_ENDIAN is not set
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# CONFIG_SH_FPU is not set
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# CONFIG_SH_FPU_EMU is not set
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CONFIG_SH_DSP=y
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CONFIG_SH_STORE_QUEUES=y
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CONFIG_CPU_HAS_INTEVT=y
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CONFIG_CPU_HAS_INTC2_IRQ=y
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CONFIG_CPU_HAS_SR_RB=y
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#
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# Board support
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#
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#
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# Timer and clock configuration
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#
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CONFIG_SH_TMU=y
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CONFIG_SH_TIMER_IRQ=16
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CONFIG_SH_PCLK_FREQ=50000000
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CONFIG_TICK_ONESHOT=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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#
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# CPU Frequency scaling
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#
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# CONFIG_CPU_FREQ is not set
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#
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# DMA support
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#
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# CONFIG_SH_DMA is not set
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#
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# Companion Chips
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#
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#
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# Additional SuperH Device Drivers
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#
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CONFIG_HEARTBEAT=y
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# CONFIG_PUSH_SWITCH is not set
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#
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# Kernel features
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#
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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# CONFIG_HZ_300 is not set
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# CONFIG_HZ_1000 is not set
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CONFIG_HZ=250
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CONFIG_KEXEC=y
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# CONFIG_CRASH_DUMP is not set
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# CONFIG_PREEMPT_NONE is not set
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# CONFIG_PREEMPT_VOLUNTARY is not set
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CONFIG_PREEMPT=y
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CONFIG_PREEMPT_BKL=y
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#
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# Boot options
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#
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CONFIG_ZERO_PAGE_OFFSET=0x00001000
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CONFIG_BOOT_LINK_OFFSET=0x00800000
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# CONFIG_UBC_WAKEUP is not set
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="console=ttySC0,115200 ip=192.168.1.2:::255.255.255.0 root=/dev/nfs nfsroot=192.168.1.1:/exports/devel/rfs/mobiler noaliencache earlyprintk=bios ignore_loglevel"
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#
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# Bus options
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#
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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#
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# PCCARD (PCMCIA/CardBus) support
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#
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# CONFIG_PCCARD is not set
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#
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# Executable file formats
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#
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CONFIG_BINFMT_ELF=y
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# CONFIG_BINFMT_MISC is not set
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#
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# Networking
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#
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# CONFIG_NET is not set
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#
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# Device Drivers
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#
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#
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# Generic Driver Options
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#
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CONFIG_STANDALONE=y
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CONFIG_PREVENT_FIRMWARE_BUILD=y
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# CONFIG_FW_LOADER is not set
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# CONFIG_DEBUG_DRIVER is not set
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# CONFIG_DEBUG_DEVRES is not set
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# CONFIG_SYS_HYPERVISOR is not set
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#
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# Connector - unified userspace <-> kernelspace linker
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#
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# CONFIG_MTD is not set
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#
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# Parallel port support
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#
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# CONFIG_PARPORT is not set
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#
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# Plug and Play support
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#
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# CONFIG_PNPACPI is not set
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#
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# Block devices
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#
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# CONFIG_BLK_DEV_COW_COMMON is not set
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# CONFIG_BLK_DEV_LOOP is not set
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_COUNT=16
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CONFIG_BLK_DEV_RAM_SIZE=4096
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CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
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# CONFIG_CDROM_PKTCDVD is not set
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#
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# Misc devices
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#
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# CONFIG_BLINK is not set
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# CONFIG_IDE is not set
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#
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# SCSI device support
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#
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# CONFIG_RAID_ATTRS is not set
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CONFIG_SCSI=y
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# CONFIG_SCSI_TGT is not set
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# CONFIG_SCSI_NETLINK is not set
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CONFIG_SCSI_PROC_FS=y
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#
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# SCSI support type (disk, tape, CD-ROM)
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#
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CONFIG_BLK_DEV_SD=y
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# CONFIG_CHR_DEV_ST is not set
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# CONFIG_CHR_DEV_OSST is not set
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# CONFIG_BLK_DEV_SR is not set
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# CONFIG_CHR_DEV_SG is not set
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# CONFIG_CHR_DEV_SCH is not set
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#
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# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
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#
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# CONFIG_SCSI_MULTI_LUN is not set
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# CONFIG_SCSI_CONSTANTS is not set
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# CONFIG_SCSI_LOGGING is not set
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# CONFIG_SCSI_SCAN_ASYNC is not set
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CONFIG_SCSI_WAIT_SCAN=m
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#
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# SCSI Transports
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#
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# CONFIG_SCSI_SPI_ATTRS is not set
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# CONFIG_SCSI_FC_ATTRS is not set
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# CONFIG_SCSI_SAS_ATTRS is not set
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# CONFIG_SCSI_SAS_LIBSAS is not set
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#
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# SCSI low-level drivers
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#
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# CONFIG_SCSI_DEBUG is not set
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CONFIG_ATA=y
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# CONFIG_ATA_NONSTANDARD is not set
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CONFIG_PATA_PLATFORM=y
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#
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# Multi-device support (RAID and LVM)
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#
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# CONFIG_MD is not set
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#
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# ISDN subsystem
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#
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#
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# Telephony Support
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#
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# CONFIG_PHONE is not set
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#
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# Input device support
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#
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CONFIG_INPUT=y
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# CONFIG_INPUT_FF_MEMLESS is not set
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#
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# Userland interfaces
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#
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CONFIG_INPUT_MOUSEDEV=y
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# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
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CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
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CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
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# CONFIG_INPUT_JOYDEV is not set
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# CONFIG_INPUT_TSDEV is not set
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# CONFIG_INPUT_EVDEV is not set
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# CONFIG_INPUT_EVBUG is not set
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#
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# Input Device Drivers
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#
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CONFIG_INPUT_KEYBOARD=y
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CONFIG_KEYBOARD_ATKBD=y
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# CONFIG_KEYBOARD_SUNKBD is not set
|
||||
# CONFIG_KEYBOARD_LKKBD is not set
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_NEWTON is not set
|
||||
# CONFIG_KEYBOARD_STOWAWAY is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
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# CONFIG_INPUT_JOYSTICK is not set
|
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# CONFIG_INPUT_TABLET is not set
|
||||
# CONFIG_INPUT_TOUCHSCREEN is not set
|
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# CONFIG_INPUT_MISC is not set
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#
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# Hardware I/O ports
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#
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CONFIG_SERIO=y
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# CONFIG_SERIO_I8042 is not set
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# CONFIG_SERIO_SERPORT is not set
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CONFIG_SERIO_LIBPS2=y
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||||
# CONFIG_SERIO_RAW is not set
|
||||
# CONFIG_GAMEPORT is not set
|
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|
||||
#
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# Character devices
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#
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||||
# CONFIG_VT is not set
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# CONFIG_SERIAL_NONSTANDARD is not set
|
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||||
#
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# Serial drivers
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#
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# CONFIG_SERIAL_8250 is not set
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||||
#
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# Non-8250 serial port support
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||||
#
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||||
CONFIG_SERIAL_SH_SCI=y
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CONFIG_SERIAL_SH_SCI_NR_UARTS=2
|
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CONFIG_SERIAL_SH_SCI_CONSOLE=y
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CONFIG_SERIAL_CORE=y
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||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
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CONFIG_UNIX98_PTYS=y
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CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
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||||
#
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# IPMI
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||||
#
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||||
# CONFIG_IPMI_HANDLER is not set
|
||||
# CONFIG_WATCHDOG is not set
|
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CONFIG_HW_RANDOM=y
|
||||
# CONFIG_R3964 is not set
|
||||
# CONFIG_RAW_DRIVER is not set
|
||||
|
||||
#
|
||||
# TPM devices
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||||
#
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||||
# CONFIG_TCG_TPM is not set
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# CONFIG_I2C is not set
|
||||
|
||||
#
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||||
# SPI support
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||||
#
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||||
# CONFIG_SPI is not set
|
||||
# CONFIG_SPI_MASTER is not set
|
||||
|
||||
#
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# Dallas's 1-wire bus
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||||
#
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||||
# CONFIG_W1 is not set
|
||||
# CONFIG_HWMON is not set
|
||||
|
||||
#
|
||||
# Multifunction device drivers
|
||||
#
|
||||
# CONFIG_MFD_SM501 is not set
|
||||
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||||
#
|
||||
# Multimedia devices
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||||
#
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||||
# CONFIG_VIDEO_DEV is not set
|
||||
# CONFIG_DAB is not set
|
||||
|
||||
#
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||||
# Graphics support
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||||
#
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||||
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
|
||||
|
||||
#
|
||||
# Display device support
|
||||
#
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||||
# CONFIG_DISPLAY_SUPPORT is not set
|
||||
# CONFIG_VGASTATE is not set
|
||||
# CONFIG_FB is not set
|
||||
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||||
#
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||||
# Sound
|
||||
#
|
||||
# CONFIG_SOUND is not set
|
||||
|
||||
#
|
||||
# HID Devices
|
||||
#
|
||||
# CONFIG_HID is not set
|
||||
|
||||
#
|
||||
# USB support
|
||||
#
|
||||
# CONFIG_USB_ARCH_HAS_HCD is not set
|
||||
# CONFIG_USB_ARCH_HAS_OHCI is not set
|
||||
# CONFIG_USB_ARCH_HAS_EHCI is not set
|
||||
|
||||
#
|
||||
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
|
||||
#
|
||||
|
||||
#
|
||||
# USB Gadget Support
|
||||
#
|
||||
# CONFIG_USB_GADGET is not set
|
||||
# CONFIG_MMC is not set
|
||||
|
||||
#
|
||||
# LED devices
|
||||
#
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
|
||||
#
|
||||
# LED drivers
|
||||
#
|
||||
|
||||
#
|
||||
# LED Triggers
|
||||
#
|
||||
|
||||
#
|
||||
# InfiniBand support
|
||||
#
|
||||
|
||||
#
|
||||
# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
|
||||
#
|
||||
|
||||
#
|
||||
# Real Time Clock
|
||||
#
|
||||
CONFIG_RTC_LIB=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_HCTOSYS=y
|
||||
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
|
||||
# CONFIG_RTC_DEBUG is not set
|
||||
|
||||
#
|
||||
# RTC interfaces
|
||||
#
|
||||
CONFIG_RTC_INTF_SYSFS=y
|
||||
CONFIG_RTC_INTF_PROC=y
|
||||
CONFIG_RTC_INTF_DEV=y
|
||||
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
|
||||
# CONFIG_RTC_DRV_TEST is not set
|
||||
|
||||
#
|
||||
# I2C RTC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# SPI RTC drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Platform RTC drivers
|
||||
#
|
||||
# CONFIG_RTC_DRV_DS1553 is not set
|
||||
# CONFIG_RTC_DRV_DS1742 is not set
|
||||
# CONFIG_RTC_DRV_M48T86 is not set
|
||||
# CONFIG_RTC_DRV_V3020 is not set
|
||||
|
||||
#
|
||||
# on-CPU RTC drivers
|
||||
#
|
||||
CONFIG_RTC_DRV_SH=y
|
||||
|
||||
#
|
||||
# DMA Engine support
|
||||
#
|
||||
# CONFIG_DMA_ENGINE is not set
|
||||
|
||||
#
|
||||
# DMA Clients
|
||||
#
|
||||
|
||||
#
|
||||
# DMA Devices
|
||||
#
|
||||
|
||||
#
|
||||
# File systems
|
||||
#
|
||||
CONFIG_EXT2_FS=y
|
||||
# CONFIG_EXT2_FS_XATTR is not set
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
# CONFIG_EXT3_FS_POSIX_ACL is not set
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
# CONFIG_EXT4DEV_FS is not set
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
# CONFIG_FS_POSIX_ACL is not set
|
||||
# CONFIG_XFS_FS is not set
|
||||
# CONFIG_GFS2_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_ROMFS_FS is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_INOTIFY_USER=y
|
||||
# CONFIG_QUOTA is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_AUTOFS_FS is not set
|
||||
# CONFIG_AUTOFS4_FS is not set
|
||||
# CONFIG_FUSE_FS is not set
|
||||
|
||||
#
|
||||
# CD-ROM/DVD Filesystems
|
||||
#
|
||||
# CONFIG_ISO9660_FS is not set
|
||||
# CONFIG_UDF_FS is not set
|
||||
|
||||
#
|
||||
# DOS/FAT/NT Filesystems
|
||||
#
|
||||
# CONFIG_MSDOS_FS is not set
|
||||
# CONFIG_VFAT_FS is not set
|
||||
# CONFIG_NTFS_FS is not set
|
||||
|
||||
#
|
||||
# Pseudo filesystems
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_TMPFS_POSIX_ACL is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_RAMFS=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
#
|
||||
# CONFIG_ADFS_FS is not set
|
||||
# CONFIG_AFFS_FS is not set
|
||||
# CONFIG_HFS_FS is not set
|
||||
# CONFIG_HFSPLUS_FS is not set
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
# CONFIG_CRAMFS is not set
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_HPFS_FS is not set
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
# CONFIG_UFS_FS is not set
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
#
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_MSDOS_PARTITION=y
|
||||
|
||||
#
|
||||
# Native Language Support
|
||||
#
|
||||
# CONFIG_NLS is not set
|
||||
|
||||
#
|
||||
# Profiling support
|
||||
#
|
||||
CONFIG_PROFILING=y
|
||||
# CONFIG_OPROFILE is not set
|
||||
|
||||
#
|
||||
# Kernel hacking
|
||||
#
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_HEADERS_CHECK is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
# CONFIG_DEBUG_SHIRQ is not set
|
||||
CONFIG_DETECT_SOFTLOCKUP=y
|
||||
# CONFIG_SCHEDSTATS is not set
|
||||
# CONFIG_TIMER_STATS is not set
|
||||
CONFIG_DEBUG_SLAB=y
|
||||
CONFIG_DEBUG_SLAB_LEAK=y
|
||||
CONFIG_DEBUG_PREEMPT=y
|
||||
# CONFIG_DEBUG_RT_MUTEXES is not set
|
||||
# CONFIG_RT_MUTEX_TESTER is not set
|
||||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_LOCK_ALLOC=y
|
||||
# CONFIG_PROVE_LOCKING is not set
|
||||
CONFIG_LOCKDEP=y
|
||||
CONFIG_DEBUG_LOCKDEP=y
|
||||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEBUG_INFO is not set
|
||||
CONFIG_DEBUG_VM=y
|
||||
# CONFIG_DEBUG_LIST is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FORCED_INLINING=y
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
# CONFIG_FAULT_INJECTION is not set
|
||||
CONFIG_SH_STANDARD_BIOS=y
|
||||
# CONFIG_EARLY_SCIF_CONSOLE is not set
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
# CONFIG_DEBUG_BOOTMEM is not set
|
||||
CONFIG_DEBUG_STACKOVERFLOW=y
|
||||
CONFIG_DEBUG_STACK_USAGE=y
|
||||
# CONFIG_4KSTACKS is not set
|
||||
# CONFIG_SH_KGDB is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Library routines
|
||||
#
|
||||
CONFIG_BITREVERSE=y
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
# CONFIG_CRC16 is not set
|
||||
# CONFIG_CRC_ITU_T is not set
|
||||
CONFIG_CRC32=y
|
||||
# CONFIG_LIBCRC32C is not set
|
||||
CONFIG_PLIST=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT=y
|
||||
CONFIG_HAS_DMA=y
|
||||
|
|
@ -340,8 +340,27 @@ ENTRY(vbr_base)
|
|||
general_exception:
|
||||
mov.l 1f, k2
|
||||
mov.l 2f, k3
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SHX3
|
||||
mov.l @k2, k2
|
||||
|
||||
! Is EXPEVT larger than 0x800?
|
||||
mov #0x8, k0
|
||||
shll8 k0
|
||||
cmp/hs k0, k2
|
||||
bf 0f
|
||||
|
||||
! then add 0x580 (k2 is 0xd80 or 0xda0)
|
||||
mov #0x58, k0
|
||||
shll2 k0
|
||||
shll2 k0
|
||||
add k0, k2
|
||||
0:
|
||||
bra handle_exception
|
||||
nop
|
||||
#else
|
||||
bra handle_exception
|
||||
mov.l @k2, k2
|
||||
#endif
|
||||
.align 2
|
||||
1: .long EXPEVT
|
||||
2: .long ret_from_exception
|
||||
|
|
|
|||
|
|
@ -141,6 +141,14 @@ int __init detect_cpu_and_cache_system(void)
|
|||
current_cpu_data.flags |= CPU_HAS_LLSC;
|
||||
}
|
||||
break;
|
||||
case 0x4000: /* 1st cut */
|
||||
case 0x4001: /* 2nd cut */
|
||||
current_cpu_data.type = CPU_SHX3;
|
||||
current_cpu_data.icache.ways = 4;
|
||||
current_cpu_data.dcache.ways = 4;
|
||||
current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
|
||||
CPU_HAS_LLSC;
|
||||
break;
|
||||
case 0x8000:
|
||||
current_cpu_data.type = CPU_ST40RA;
|
||||
current_cpu_data.flags |= CPU_HAS_FPU;
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
|
|||
obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
|
||||
|
||||
# Primary on-chip clocks (common)
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o
|
||||
|
|
@ -17,5 +18,6 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
|
|||
clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
|
||||
|
||||
obj-y += $(clock-y)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* arch/sh/kernel/cpu/sh4/clock-shx3.c
|
||||
*
|
||||
* SH-X3 support for the clock framework
|
||||
*
|
||||
* Copyright (C) 2006-2007 Renesas Technology Corp.
|
||||
* Copyright (C) 2006-2007 Renesas Solutions Corp.
|
||||
* Copyright (C) 2006-2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/freq.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int ifc_divisors[] = { 1, 2, 4 ,6 };
|
||||
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
|
||||
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
|
||||
static int cfc_divisors[] = { 1, 1, 4, 6 };
|
||||
|
||||
#define IFC_POS 28
|
||||
#define IFC_MSK 0x0003
|
||||
#define BFC_MSK 0x000f
|
||||
#define PFC_MSK 0x000f
|
||||
#define CFC_MSK 0x0003
|
||||
#define BFC_POS 16
|
||||
#define PFC_POS 0
|
||||
#define CFC_POS 20
|
||||
|
||||
static void master_clk_init(struct clk *clk)
|
||||
{
|
||||
clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
|
||||
}
|
||||
|
||||
static struct clk_ops shx3_master_clk_ops = {
|
||||
.init = master_clk_init,
|
||||
};
|
||||
|
||||
static void module_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
|
||||
clk->rate = clk->parent->rate / pfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops shx3_module_clk_ops = {
|
||||
.recalc = module_clk_recalc,
|
||||
};
|
||||
|
||||
static void bus_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
|
||||
clk->rate = clk->parent->rate / bfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops shx3_bus_clk_ops = {
|
||||
.recalc = bus_clk_recalc,
|
||||
};
|
||||
|
||||
static void cpu_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
|
||||
clk->rate = clk->parent->rate / ifc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops shx3_cpu_clk_ops = {
|
||||
.recalc = cpu_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk_ops *shx3_clk_ops[] = {
|
||||
&shx3_master_clk_ops,
|
||||
&shx3_module_clk_ops,
|
||||
&shx3_bus_clk_ops,
|
||||
&shx3_cpu_clk_ops,
|
||||
};
|
||||
|
||||
void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
|
||||
{
|
||||
if (idx < ARRAY_SIZE(shx3_clk_ops))
|
||||
*ops = shx3_clk_ops[idx];
|
||||
}
|
||||
|
||||
static void shyway_clk_recalc(struct clk *clk)
|
||||
{
|
||||
int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
|
||||
clk->rate = clk->parent->rate / cfc_divisors[idx];
|
||||
}
|
||||
|
||||
static struct clk_ops shx3_shyway_clk_ops = {
|
||||
.recalc = shyway_clk_recalc,
|
||||
};
|
||||
|
||||
static struct clk shx3_shyway_clk = {
|
||||
.name = "shyway_clk",
|
||||
.flags = CLK_ALWAYS_ENABLED,
|
||||
.ops = &shx3_shyway_clk_ops,
|
||||
};
|
||||
|
||||
/*
|
||||
* Additional SHx3-specific on-chip clocks that aren't already part of the
|
||||
* clock framework
|
||||
*/
|
||||
static struct clk *shx3_onchip_clocks[] = {
|
||||
&shx3_shyway_clk,
|
||||
};
|
||||
|
||||
static int __init shx3_clk_init(void)
|
||||
{
|
||||
struct clk *clk = clk_get(NULL, "master_clk");
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
|
||||
struct clk *clkp = shx3_onchip_clocks[i];
|
||||
|
||||
clkp->parent = clk;
|
||||
clk_register(clkp);
|
||||
clk_enable(clkp);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that we have the rest of the clocks registered, we need to
|
||||
* force the parent clock to propagate so that these clocks will
|
||||
* automatically figure out their rate. We cheat by handing the
|
||||
* parent clock its current rate and forcing child propagation.
|
||||
*/
|
||||
clk_set_rate(clk, clk_get_rate(clk));
|
||||
|
||||
clk_put(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(shx3_clk_init);
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* SH-X3 Setup
|
||||
*
|
||||
* Copyright (C) 2007 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/sci.h>
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffc30000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 40, 41, 43, 42 },
|
||||
}, {
|
||||
.mapbase = 0xffc40000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 44, 45, 47, 46 },
|
||||
}, {
|
||||
.mapbase = 0xffc50000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 48, 49, 51, 50 },
|
||||
}, {
|
||||
.mapbase = 0xffc60000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 52, 53, 55, 54 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *shx3_devices[] __initdata = {
|
||||
&sci_device,
|
||||
};
|
||||
|
||||
static int __init shx3_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(shx3_devices,
|
||||
ARRAY_SIZE(shx3_devices));
|
||||
}
|
||||
__initcall(shx3_devices_setup);
|
||||
|
||||
static struct intc2_data intc2_irq_table[] = {
|
||||
{ 16, 0, 0, 0, 1, 2 }, /* TMU0 */
|
||||
{ 40, 4, 0, 0x20, 0, 3 }, /* SCIF0 ERI */
|
||||
{ 41, 4, 0, 0x20, 1, 3 }, /* SCIF0 RXI */
|
||||
{ 42, 4, 0, 0x20, 2, 3 }, /* SCIF0 BRI */
|
||||
{ 43, 4, 0, 0x20, 3, 3 }, /* SCIF0 TXI */
|
||||
};
|
||||
|
||||
static struct intc2_desc intc2_irq_desc __read_mostly = {
|
||||
.prio_base = 0xfe410000,
|
||||
.msk_base = 0xfe410820,
|
||||
.mskclr_base = 0xfe410850,
|
||||
|
||||
.intc2_data = intc2_irq_table,
|
||||
.nr_irqs = ARRAY_SIZE(intc2_irq_table),
|
||||
|
||||
.chip = {
|
||||
.name = "INTC2-SHX3",
|
||||
},
|
||||
};
|
||||
|
||||
void __init init_IRQ_intc2(void)
|
||||
{
|
||||
register_intc2_controller(&intc2_irq_desc);
|
||||
}
|
||||
|
|
@ -285,7 +285,7 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
|
||||
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
|
||||
[CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722",
|
||||
[CPU_SH_NONE] = "Unknown"
|
||||
[CPU_SHX3] = "SH-X3", [CPU_SH_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
const char *get_cpu_subtype(struct sh_cpuinfo *c)
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
static int tmu_timer_start(void)
|
||||
{
|
||||
ctrl_outb(ctrl_inb(TMU_TSTR) | 0x3, TMU_TSTR);
|
||||
ctrl_outb(ctrl_inb(TMU_012_TSTR) | 0x3, TMU_012_TSTR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload)
|
|||
|
||||
static int tmu_timer_stop(void)
|
||||
{
|
||||
ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x3, TMU_TSTR);
|
||||
ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~0x3, TMU_012_TSTR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -174,7 +174,8 @@ static int tmu_timer_init(void)
|
|||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
|
||||
!defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,9 @@ config CPU_SUBTYPE_ST40
|
|||
config CPU_SHX2
|
||||
bool
|
||||
|
||||
config CPU_SHX3
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Processor sub-type selection"
|
||||
|
||||
|
|
@ -193,6 +196,12 @@ config CPU_SUBTYPE_SH7785
|
|||
select CPU_SHX2
|
||||
select CPU_HAS_INTC2_IRQ
|
||||
|
||||
config CPU_SUBTYPE_SHX3
|
||||
bool "Support SH-X3 processor"
|
||||
select CPU_SH4A
|
||||
select CPU_SHX3
|
||||
select CPU_HAS_INTC2_IRQ
|
||||
|
||||
# SH4AL-DSP Processor Support
|
||||
|
||||
config CPU_SUBTYPE_SH73180
|
||||
|
|
|
|||
|
|
@ -367,7 +367,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
} else {
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7343
|
||||
/* Nothing */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
|
||||
#else
|
||||
ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@
|
|||
# define SCPDR 0xA4050136 /* 16 bit SCIF */
|
||||
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
|
||||
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
|
||||
# define SCI_NPORTS 2
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
|
|
@ -173,6 +173,14 @@
|
|||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
|
||||
# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
|
||||
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#else
|
||||
# error CPU subtype not defined
|
||||
#endif
|
||||
|
|
@ -189,7 +197,8 @@
|
|||
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
|
||||
#else
|
||||
#define SCI_CTRL_FLAGS_REIE 0
|
||||
|
|
@ -666,6 +675,18 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffc30000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffc40000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffc50000)
|
||||
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffc60000)
|
||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static void __init check_bugs(void)
|
|||
case CPU_SH7750 ... CPU_SH4_501:
|
||||
*p++ = '4';
|
||||
break;
|
||||
case CPU_SH7770 ... CPU_SH7785:
|
||||
case CPU_SH7770 ... CPU_SHX3:
|
||||
*p++ = '4';
|
||||
*p++ = 'a';
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#define FRQCR0 0xffc80000
|
||||
#define FRQCR1 0xffc80004
|
||||
#define FRQMR1 0xffc80014
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
#define FRQCR 0xffc00014
|
||||
#else
|
||||
#define FRQCR 0xffc00000
|
||||
#define FRQCR_PSTBY 0x0200
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* include/asm-sh/cpu-sh4/timer.h
|
||||
*
|
||||
* Copyright (C) 2004 Lineo Solutions, Inc.
|
||||
* Copyright (C) 2004 Lineo Solutions, Inc.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
|
|
@ -16,36 +16,45 @@
|
|||
* SH7750S/SH7750R
|
||||
* SH7751/SH7751R
|
||||
* SH7760
|
||||
* SH-X3
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
#define TMU_TOCR 0xffd80000 /* Byte access */
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SHX3
|
||||
#define TMU_012_BASE 0xffc10000
|
||||
#define TMU_345_BASE 0xffc20000
|
||||
#else
|
||||
#define TMU_012_BASE 0xffd80000
|
||||
#define TMU_345_BASE 0xfe100000
|
||||
#endif
|
||||
#define TMU_TSTR 0xffd80004 /* Byte access */
|
||||
|
||||
#define TMU0_TCOR 0xffd80008 /* Long access */
|
||||
#define TMU0_TCNT 0xffd8000c /* Long access */
|
||||
#define TMU0_TCR 0xffd80010 /* Word access */
|
||||
#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
|
||||
|
||||
#define TMU1_TCOR 0xffd80014 /* Long access */
|
||||
#define TMU1_TCNT 0xffd80018 /* Long access */
|
||||
#define TMU1_TCR 0xffd8001c /* Word access */
|
||||
#define TMU_012_TSTR (TMU_012_BASE + 0x04)
|
||||
#define TMU_345_TSTR (TMU_345_BASE + 0x04)
|
||||
|
||||
#define TMU2_TCOR 0xffd80020 /* Long access */
|
||||
#define TMU2_TCNT 0xffd80024 /* Long access */
|
||||
#define TMU2_TCR 0xffd80028 /* Word access */
|
||||
#define TMU2_TCPR 0xffd8002c /* Long access */
|
||||
#define TMU0_TCOR (TMU_012_BASE + 0x08)
|
||||
#define TMU0_TCNT (TMU_012_BASE + 0x0c)
|
||||
#define TMU0_TCR (TMU_012_BASE + 0x10)
|
||||
|
||||
#if !defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||
#define TMU3_TCOR 0xfe100008 /* Long access */
|
||||
#define TMU3_TCNT 0xfe10000c /* Long access */
|
||||
#define TMU3_TCR 0xfe100010 /* Word access */
|
||||
#define TMU1_TCOR (TMU_012_BASE + 0x14)
|
||||
#define TMU1_TCNT (TMU_012_BASE + 0x18)
|
||||
#define TMU1_TCR (TMU_012_BASE + 0x1c)
|
||||
|
||||
#define TMU4_TCOR 0xfe100014 /* Long access */
|
||||
#define TMU4_TCNT 0xfe100018 /* Long access */
|
||||
#define TMU4_TCR 0xfe10001c /* Word access */
|
||||
#endif
|
||||
#define TMU2_TCOR (TMU_012_BASE + 0x20)
|
||||
#define TMU2_TCNT (TMU_012_BASE + 0x24)
|
||||
#define TMU2_TCR (TMU_012_BASE + 0x28)
|
||||
#define TMU2_TCPR (TMU_012_BASE + 0x2c)
|
||||
|
||||
#define TMU3_TCOR (TMU_345_BASE + 0x08)
|
||||
#define TMU3_TCNT (TMU_345_BASE + 0x0c)
|
||||
#define TMU3_TCR (TMU_345_BASE + 0x10)
|
||||
|
||||
#define TMU4_TCOR (TMU_345_BASE + 0x14)
|
||||
#define TMU4_TCNT (TMU_345_BASE + 0x18)
|
||||
#define TMU4_TCR (TMU_345_BASE + 0x1c)
|
||||
|
||||
#define TMU5_TCOR (TMU_345_BASE + 0x20)
|
||||
#define TMU5_TCNT (TMU_345_BASE + 0x24)
|
||||
#define TMU5_TCR (TMU_345_BASE + 0x28)
|
||||
|
||||
#endif /* __ASM_CPU_SH4_TIMER_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ enum cpu_type {
|
|||
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
|
||||
|
||||
/* SH-4A types */
|
||||
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
|
||||
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
|
||||
|
||||
/* SH4AL-DSP types */
|
||||
CPU_SH73180, CPU_SH7343, CPU_SH7722,
|
||||
|
|
|
|||
Loading…
Reference in New Issue